]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/xe/xe2: Add workaround 14021402888
authorBommu Krishnaiah <krishnaiah.bommu@intel.com>
Thu, 18 Apr 2024 11:15:34 +0000 (16:45 +0530)
committerLucas De Marchi <lucas.demarchi@intel.com>
Wed, 8 May 2024 21:24:50 +0000 (14:24 -0700)
This workaround applies to Graphics 20.01 as RCS engine workaround

Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240418111534.481568-1-krishnaiah.bommu@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_wa.c

index 8f44437c8e02a368b1baea49ae160626194090c3..9cacdcfe27ffe36b76eb04dfd1eea58f4713dbdd 100644 (file)
 
 #define HALF_SLICE_CHICKEN7                            XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA      REG_BIT(15)
+#define   CLEAR_OPTIMIZATION_DISABLE                   REG_BIT(6)
 
 #define CACHE_MODE_SS                          XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
 #define   DISABLE_ECC                          REG_BIT(5)
index 134a34dbfe8d8534c9fbe299ed578af5df80878f..05db53c1448c5acc945d2d1643cc409365c189cc 100644 (file)
@@ -533,6 +533,10 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
        },
+       { XE_RTP_NAME("14021402888"),
+         XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
+         XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
+       },
 
        /* Xe2_HPM */