KVM: arm64: Add basic support for POR_EL2

S1POE support implies support for POR_EL2, which  we provide by

- adding it to the vcpu_sysreg enum
- advertising it as mapped to its EL1 counterpart in get_el2_to_el1_mapping
- wiring it in the sys_reg_desc table with the correct visibility
- handling POR_EL1 in __vcpu_{read,write}_sys_reg_from_cpu()

Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241023145345.1613824-32-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 9269d893f85bb8f97e4692ddf79947c95ba69bc1..28ea7e72477c018d89f56b3681df675f708cbf81 100644 (file)
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -480,6 +480,7 @@ enum vcpu_sysreg {
        TCR_EL2,        /* Translation Control Register (EL2) */
        PIRE0_EL2,      /* Permission Indirection Register 0 (EL2) */
        PIR_EL2,        /* Permission Indirection Register 1 (EL2) */
+       POR_EL2,        /* Permission Overlay Register 2 (EL2) */
        SPSR_EL2,       /* EL2 saved program status register */
        ELR_EL2,        /* EL2 exception link register */
        AFSR0_EL2,      /* Auxiliary Fault Status Register 0 (EL2) */
@@ -1050,6 +1051,7 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
        case TCR2_EL1:          *val = read_sysreg_s(SYS_TCR2_EL12);    break;
        case PIR_EL1:           *val = read_sysreg_s(SYS_PIR_EL12);     break;
        case PIRE0_EL1:         *val = read_sysreg_s(SYS_PIRE0_EL12);   break;
+       case POR_EL1:           *val = read_sysreg_s(SYS_POR_EL12);     break;
        case ESR_EL1:           *val = read_sysreg_s(SYS_ESR_EL12);     break;
        case AFSR0_EL1:         *val = read_sysreg_s(SYS_AFSR0_EL12);   break;
        case AFSR1_EL1:         *val = read_sysreg_s(SYS_AFSR1_EL12);   break;
@@ -1099,6 +1101,7 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
        case TCR2_EL1:          write_sysreg_s(val, SYS_TCR2_EL12);     break;
        case PIR_EL1:           write_sysreg_s(val, SYS_PIR_EL12);      break;
        case PIRE0_EL1:         write_sysreg_s(val, SYS_PIRE0_EL12);    break;
+       case POR_EL1:           write_sysreg_s(val, SYS_POR_EL12);      break;
        case ESR_EL1:           write_sysreg_s(val, SYS_ESR_EL12);      break;
        case AFSR0_EL1:         write_sysreg_s(val, SYS_AFSR0_EL12);    break;
        case AFSR1_EL1:         write_sysreg_s(val, SYS_AFSR1_EL12);    break;

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d46663f27fbaa62c6df97ffed91a36d5299c8136..4f4fe84fb0e8771c3a97d0d7d482be0c373c673c 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -137,6 +137,7 @@ static bool get_el2_to_el1_mapping(unsigned int reg,
                MAPPED_EL2_SYSREG(TCR2_EL2,    TCR2_EL1,    NULL             );
                MAPPED_EL2_SYSREG(PIR_EL2,     PIR_EL1,     NULL             );
                MAPPED_EL2_SYSREG(PIRE0_EL2,   PIRE0_EL1,   NULL             );
+               MAPPED_EL2_SYSREG(POR_EL2,     POR_EL1,     NULL             );
                MAPPED_EL2_SYSREG(AMAIR_EL2,   AMAIR_EL1,   NULL             );
                MAPPED_EL2_SYSREG(ELR_EL2,     ELR_EL1,     NULL             );
                MAPPED_EL2_SYSREG(SPSR_EL2,    SPSR_EL1,    NULL             );
@@ -2329,6 +2330,12 @@ static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu,
        return REG_HIDDEN;
 }
 
+static unsigned int s1poe_el2_visibility(const struct kvm_vcpu *vcpu,
+                                        const struct sys_reg_desc *rd)
+{
+       return __el2_visibility(vcpu, rd, s1poe_visibility);
+}
+
 static unsigned int tcr2_visibility(const struct kvm_vcpu *vcpu,
                                    const struct sys_reg_desc *rd)
 {
@@ -2942,6 +2949,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
                         s1pie_el2_visibility),
        EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0,
                         s1pie_el2_visibility),
+       EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0,
+                        s1poe_el2_visibility),
        EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
 
        EL2_REG(VBAR_EL2, access_rw, reset_val, 0),