drm/xe/xe2hpg: Add Wa_18041344222 for Xe2_HPG

Add Wa_18041344222 for Xe2_HPG that requires disabling
the perf mode for subslice count for eustall sampling
when the enabled slices are discontiguous.

Bspec: 79483, 56024
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/b6a631a13a9fb7360e89d679e0797fae42d5a09e.1756855529.git.harish.chegondi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index f96b2e2b30645de3e6efb8ba3c791d407af51960..06cb6b02ec64cdfae156e0ce56df08a5bccccc82 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -522,6 +522,7 @@
 
 #define TDL_CHICKEN                            XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)
 #define   QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE  REG_BIT(12)
+#define   EUSTALL_PERF_SAMPLING_DISABLE                REG_BIT(5)
 
 #define LSC_CHICKEN_BIT_0                      XE_REG_MCR(0xe7c8)
 #define   DISABLE_D8_D16_COASLESCE             REG_BIT(30)

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
index a0baa560dd71e1a386fb9c82abc62f83390f7574..0ed7dc9044a574ba54c4c402a34117a4180e5b2a 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_topology.c
+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
@@ -12,6 +12,7 @@
 #include "regs/xe_gt_regs.h"
 #include "xe_assert.h"
 #include "xe_gt.h"
+#include "xe_gt_mcr.h"
 #include "xe_gt_printk.h"
 #include "xe_mmio.h"
 #include "xe_wa.h"
@@ -328,3 +329,19 @@ bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss)
 {
        return test_bit(dss, gt->fuse_topo.c_dss_mask);
 }
+
+bool xe_gt_has_discontiguous_dss_groups(const struct xe_gt *gt)
+{
+       unsigned int xecore;
+       int last_group = -1;
+       u16 group, instance;
+
+       for_each_dss_steering(xecore, gt, group, instance) {
+               if (last_group != group) {
+                       if (group - last_group > 1)
+                               return true;
+                       last_group = group;
+               }
+       }
+       return false;
+}

diff --git a/drivers/gpu/drm/xe/xe_gt_topology.h b/drivers/gpu/drm/xe/xe_gt_topology.h
index c8140704ad4c1411f61358fd34c9a2a44ade308b..d95cdd6e45be6b3c8cb01a92e2924b64e6f79be7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_topology.h
+++ b/drivers/gpu/drm/xe/xe_gt_topology.h
@@ -47,4 +47,6 @@ xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad);
 bool xe_gt_has_geometry_dss(struct xe_gt *gt, unsigned int dss);
 bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss);
 
+bool xe_gt_has_discontiguous_dss_groups(const struct xe_gt *gt);
+
 #endif /* _XE_GT_TOPOLOGY_H_ */

diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 47ea1521dc80c7a80c9d1d6ffbe9ff3cf17ce13b..b5f430d59f8055758adbfc45b50d06fcce4cb3d3 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -370,3 +370,9 @@ bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
 {
        return xe_configfs_get_psmi_enabled(to_pci_dev(gt_to_xe(gt)->drm.dev));
 }
+
+bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
+                                                 const struct xe_hw_engine *hwe)
+{
+       return xe_gt_has_discontiguous_dss_groups(gt);
+}

diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 7951fefdbe044a649692ffe3d294fe7388c406f8..ac12ddf6cde6d1d4dff2e4f5e071173c34c52e90 100644 (file)
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -480,4 +480,7 @@ bool xe_rtp_match_not_sriov_vf(const struct xe_gt *gt,
 bool xe_rtp_match_psmi_enabled(const struct xe_gt *gt,
                               const struct xe_hw_engine *hwe);
 
+bool xe_rtp_match_gt_has_discontiguous_dss_groups(const struct xe_gt *gt,
+                                                 const struct xe_hw_engine *hwe);
+
 #endif

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index e53edf1e5100cd5d574f8d3ebdb6921a65441ffb..c1fec526bed080cc22c4d00cc1c18112d9be0ca1 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -612,6 +612,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
                       FUNC(xe_rtp_match_first_render_or_compute)),
          XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))
        },
+       { XE_RTP_NAME("18041344222"),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002),
+                      FUNC(xe_rtp_match_first_render_or_compute),
+                      FUNC(xe_rtp_match_not_sriov_vf),
+                      FUNC(xe_rtp_match_gt_has_discontiguous_dss_groups)),
+         XE_RTP_ACTIONS(SET(TDL_CHICKEN, EUSTALL_PERF_SAMPLING_DISABLE))
+       },
 
        /* Xe2_LPM */