return PTR_ERR(cdclk_state);
 
                /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-               if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
+               if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)
                        return 0;
        }
 
 
                     "Unknown platform. Assuming i830\n"))
                display->funcs.cdclk = &i830_cdclk_funcs;
 }
+
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
+{
+       return cdclk_state->logical.cdclk;
+}
 
 int intel_cdclk_init(struct intel_display *display);
 void intel_cdclk_debugfs_register(struct intel_display *display);
 
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
+
 #endif /* __INTEL_CDCLK_H__ */
 
                return 0;
 
        linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
-                                       cdclk_state->logical.cdclk);
+                                       intel_cdclk_logical(cdclk_state));
 
        return min(linetime_wm, 0x1ff);
 }
 
                if (IS_ERR(cdclk_state))
                        return PTR_ERR(cdclk_state);
 
-               if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
+               if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
                        plane_state->no_fbc_reason = "pixel rate too high";
                        return 0;
                }
 
        }
 
        return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-                                  2 * cdclk_state->logical.cdclk));
+                                  2 * intel_cdclk_logical(cdclk_state)));
 }
 
 static int