* RFCSR 7:
  */
 #define RFCSR7_RF_TUNING               FIELD8(0x01)
-#define RFCSR7_R02                             FIELD8(0x07)
-#define RFCSR7_R3                              FIELD8(0x08)
-#define RFCSR7_R45                             FIELD8(0x30)
-#define RFCSR7_R67                             FIELD8(0xc0)
+#define RFCSR7_BIT1                    FIELD8(0x02)
+#define RFCSR7_BIT2                    FIELD8(0x04)
+#define RFCSR7_BIT3                    FIELD8(0x08)
+#define RFCSR7_BIT4                    FIELD8(0x10)
+#define RFCSR7_BIT5                    FIELD8(0x20)
+#define RFCSR7_BITS67                  FIELD8(0xc0)
 
 /*
  * RFCSR 11:
 
                rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
                rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
        } else {
-               rt2800_rfcsr_write(rt2x00dev, 7, 0x14);
+               rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
+               rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
+               rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
                rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
                rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
                rt2800_rfcsr_write(rt2x00dev, 11, 0x00);