smsc911x: enforce read-after-write timing restriction on eeprom access

The LAN911x datasheet specifies a minimum delay of 45ns between a write
of E2P_DATA and any read.  This patch adds a single dummy read of
BYTE_TEST to enforce this timing constraint.

Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c
index ad3cbc91a8fa6f45ee2a51cdc2d4014d8483fca6..af8f60ca0f57235f57abdb82cea9437b03d2d804 100644 (file)
--- a/drivers/net/smsc911x.c
+++ b/drivers/net/smsc911x.c
@@ -1680,6 +1680,7 @@ static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
                                          u8 address, u8 data)
 {
        u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
+       u32 temp;
        int ret;
 
        SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
@@ -1688,6 +1689,10 @@ static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
        if (!ret) {
                op = E2P_CMD_EPC_CMD_WRITE_ | address;
                smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
+
+               /* Workaround for hardware read-after-write restriction */
+               temp = smsc911x_reg_read(pdata, BYTE_TEST);
+
                ret = smsc911x_eeprom_send_cmd(pdata, op);
        }