#define AMDGPU_PRODUCT_NAME_LEN 64
 struct amdgpu_reset_domain;
 
+/*
+ * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
+ */
+#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
+
 struct amdgpu_device {
        struct device                   *dev;
        struct pci_dev                  *pdev;
 
 static int amdgpu_device_vram_scratch_init(struct amdgpu_device *adev)
 {
        return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
-                                      PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+                                      PAGE_SIZE,
+                                      AMDGPU_GEM_DOMAIN_VRAM,
                                       &adev->vram_scratch.robj,
                                       &adev->vram_scratch.gpu_addr,
                                       (void **)&adev->vram_scratch.ptr);
                        /* right after GMC hw init, we create CSA */
                        if (amdgpu_mcbp) {
                                r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
-                                                               AMDGPU_GEM_DOMAIN_VRAM,
-                                                               AMDGPU_CSA_SIZE);
+                                                              AMDGPU_GEM_DOMAIN_VRAM |
+                                                              AMDGPU_GEM_DOMAIN_GTT,
+                                                              AMDGPU_CSA_SIZE);
                                if (r) {
                                        DRM_ERROR("allocate CSA failed %d\n", r);
                                        goto init_failed;
 
                 * KIQ MQD no matter SRIOV or Bare-metal
                 */
                r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE,
-                                           AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj,
-                                           &ring->mqd_gpu_addr, &ring->mqd_ptr);
+                                           AMDGPU_GEM_DOMAIN_VRAM |
+                                           AMDGPU_GEM_DOMAIN_GTT,
+                                           &ring->mqd_obj,
+                                           &ring->mqd_gpu_addr,
+                                           &ring->mqd_ptr);
                if (r) {
                        dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r);
                        return r;
 
        /* allocate 4k Page of Local Frame Buffer memory for ring */
        ring->ring_size = 0x1000;
        ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
-                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->firmware.rbuf,
                                      &ring->ring_mem_mc_addr,
                                      (void **)&ring->ring_mem);
 
        if (!psp->tmr_bo) {
                pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
-               ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
-                                             AMDGPU_GEM_DOMAIN_VRAM,
-                                             &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
+               ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
+                                             PSP_TMR_ALIGNMENT,
+                                             AMDGPU_HAS_VRAM(psp->adev) ?
+                                             AMDGPU_GEM_DOMAIN_VRAM :
+                                             AMDGPU_GEM_DOMAIN_GTT,
+                                             &psp->tmr_bo, &psp->tmr_mc_addr,
+                                             pptr);
        }
 
        return ret;
        * physical) for ta to host memory
        */
        return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
-                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &mem_ctx->shared_bo,
                                      &mem_ctx->shared_mc_addr,
                                      &mem_ctx->shared_buf);
 
        /* LFB address which is aligned to 1MB boundary per PSP request */
        ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
-                                               AMDGPU_GEM_DOMAIN_VRAM,
-                                               &fw_buf_bo,
-                                               &fw_pri_mc_addr,
-                                               &fw_pri_cpu_addr);
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
+                                     &fw_buf_bo, &fw_pri_mc_addr,
+                                     &fw_pri_cpu_addr);
        if (ret)
                goto rel_buf;
 
 
 
        /* allocate save restore block */
        r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
-                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.rlc.save_restore_obj,
                                      &adev->gfx.rlc.save_restore_gpu_addr,
                                      (void **)&adev->gfx.rlc.sr_ptr);
        /* allocate clear state block */
        adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev);
        r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
-                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.rlc.clear_state_obj,
                                      &adev->gfx.rlc.clear_state_gpu_addr,
                                      (void **)&adev->gfx.rlc.cs_ptr);
        int r;
 
        r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
-                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.rlc.cp_table_obj,
                                      &adev->gfx.rlc.cp_table_gpu_addr,
                                      (void **)&adev->gfx.rlc.cp_table_ptr);
 
                /* reserve vram for mem train according to TMR location */
                amdgpu_ttm_training_data_block_init(adev);
                ret = amdgpu_bo_create_kernel_at(adev,
-                                        ctx->c2p_train_data_offset,
-                                        ctx->train_data_size,
-                                        &ctx->c2p_bo,
-                                        NULL);
+                                                ctx->c2p_train_data_offset,
+                                                ctx->train_data_size,
+                                                &ctx->c2p_bo,
+                                                NULL);
                if (ret) {
                        DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
                        amdgpu_ttm_training_reserve_vram_fini(adev);
        }
 
        ret = amdgpu_bo_create_kernel_at(adev,
-                               adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
-                               adev->mman.discovery_tmr_size,
-                               &adev->mman.discovery_memory,
-                               NULL);
+                                        adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
+                                        adev->mman.discovery_tmr_size,
+                                        &adev->mman.discovery_memory,
+                                        NULL);
        if (ret) {
                DRM_ERROR("alloc tmr failed(%d)!\n", ret);
                amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
 
                if (adev->uvd.harvest_config & (1 << j))
                        continue;
                r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
-                                           AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
-                                           &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr);
+                                           AMDGPU_GEM_DOMAIN_VRAM |
+                                           AMDGPU_GEM_DOMAIN_GTT,
+                                           &adev->uvd.inst[j].vcpu_bo,
+                                           &adev->uvd.inst[j].gpu_addr,
+                                           &adev->uvd.inst[j].cpu_addr);
                if (r) {
                        dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
                        return r;
 
                                (binary_id << 8));
 
        r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE,
-                                   AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo,
+                                   AMDGPU_GEM_DOMAIN_VRAM |
+                                   AMDGPU_GEM_DOMAIN_GTT,
+                                   &adev->vce.vcpu_bo,
                                    &adev->vce.gpu_addr, &adev->vce.cpu_addr);
        if (r) {
                dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
 
                        continue;
 
                r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
-                                               AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].vcpu_bo,
-                                               &adev->vcn.inst[i].gpu_addr, &adev->vcn.inst[i].cpu_addr);
+                                           AMDGPU_GEM_DOMAIN_VRAM |
+                                           AMDGPU_GEM_DOMAIN_GTT,
+                                           &adev->vcn.inst[i].vcpu_bo,
+                                           &adev->vcn.inst[i].gpu_addr,
+                                           &adev->vcn.inst[i].cpu_addr);
                if (r) {
                        dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
                        return r;
 
                if (adev->vcn.indirect_sram) {
                        r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
-                                       AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].dpg_sram_bo,
-                                       &adev->vcn.inst[i].dpg_sram_gpu_addr, &adev->vcn.inst[i].dpg_sram_cpu_addr);
+                                       AMDGPU_GEM_DOMAIN_VRAM |
+                                       AMDGPU_GEM_DOMAIN_GTT,
+                                       &adev->vcn.inst[i].dpg_sram_bo,
+                                       &adev->vcn.inst[i].dpg_sram_gpu_addr,
+                                       &adev->vcn.inst[i].dpg_sram_cpu_addr);
                        if (r) {
                                dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
                                return r;
 
                return 0;
 
        r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
-                                   AMDGPU_GEM_DOMAIN_VRAM,
+                                   AMDGPU_GEM_DOMAIN_VRAM |
+                                   AMDGPU_GEM_DOMAIN_GTT,
                                    &adev->virt.mm_table.bo,
                                    &adev->virt.mm_table.gpu_addr,
                                    (void *)&adev->virt.mm_table.cpu_addr);
 
        total_size = gfx_v11_0_calc_toc_total_size(adev);
 
        r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
-                       AMDGPU_GEM_DOMAIN_VRAM,
-                       &adev->gfx.rlc.rlc_autoload_bo,
-                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
-                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
+                                     &adev->gfx.rlc.rlc_autoload_bo,
+                                     &adev->gfx.rlc.rlc_autoload_gpu_addr,
+                                     (void **)&adev->gfx.rlc.rlc_autoload_ptr);
 
        if (r) {
                dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
 
        /* 64kb align */
        r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
-                                     64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+                                     64 * 1024,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.pfp.pfp_fw_obj,
                                      &adev->gfx.pfp.pfp_fw_gpu_addr,
                                      (void **)&adev->gfx.pfp.pfp_fw_ptr);
        }
 
        r = amdgpu_bo_create_reserved(adev, fw_data_size,
-                                     64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+                                     64 * 1024,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.pfp.pfp_fw_data_obj,
                                      &adev->gfx.pfp.pfp_fw_data_gpu_addr,
                                      (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
 
        /* 64kb align*/
        r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
-                                     64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+                                     64 * 1024,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.me.me_fw_obj,
                                      &adev->gfx.me.me_fw_gpu_addr,
                                      (void **)&adev->gfx.me.me_fw_ptr);
        }
 
        r = amdgpu_bo_create_reserved(adev, fw_data_size,
-                                     64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+                                     64 * 1024,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.me.me_fw_data_obj,
                                      &adev->gfx.me.me_fw_data_gpu_addr,
                                      (void **)&adev->gfx.me.me_fw_data_ptr);
        fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
 
        r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
-                                     64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+                                     64 * 1024,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.mec.mec_fw_obj,
                                      &adev->gfx.mec.mec_fw_gpu_addr,
                                      (void **)&fw_ucode_ptr);
        }
 
        r = amdgpu_bo_create_reserved(adev, fw_data_size,
-                                     64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+                                     64 * 1024,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.mec.mec_fw_data_obj,
                                      &adev->gfx.mec.mec_fw_data_gpu_addr,
                                      (void **)&fw_data_ptr);
 
                dws = adev->gfx.rlc.clear_state_size + (256 / 4);
 
                r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
-                                             AMDGPU_GEM_DOMAIN_VRAM,
+                                             AMDGPU_GEM_DOMAIN_VRAM |
+                                             AMDGPU_GEM_DOMAIN_GTT,
                                              &adev->gfx.rlc.clear_state_obj,
                                              &adev->gfx.rlc.clear_state_gpu_addr,
                                              (void **)&adev->gfx.rlc.cs_ptr);
 
                * GFX7_MEC_HPD_SIZE * 2;
 
        r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
-                                     AMDGPU_GEM_DOMAIN_VRAM,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->gfx.mec.hpd_eop_obj,
                                      &adev->gfx.mec.hpd_eop_gpu_addr,
                                      (void **)&hpd);
 
        mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE;
        if (mec_hpd_size) {
                r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
-                                             AMDGPU_GEM_DOMAIN_VRAM,
+                                             AMDGPU_GEM_DOMAIN_VRAM |
+                                             AMDGPU_GEM_DOMAIN_GTT,
                                              &adev->gfx.mec.hpd_eop_obj,
                                              &adev->gfx.mec.hpd_eop_gpu_addr,
                                              (void **)&hpd);
 
        mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
        if (mec_hpd_size) {
                r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
-                                             AMDGPU_GEM_DOMAIN_VRAM,
+                                             AMDGPU_GEM_DOMAIN_VRAM |
+                                             AMDGPU_GEM_DOMAIN_GTT,
                                              &adev->gfx.mec.hpd_eop_obj,
                                              &adev->gfx.mec.hpd_eop_gpu_addr,
                                              (void **)&hpd);
 
        fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
 
        r = amdgpu_bo_create_reserved(adev, fw_size,
-                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
+                                     PAGE_SIZE,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->mes.ucode_fw_obj[pipe],
                                      &adev->mes.ucode_fw_gpu_addr[pipe],
                                      (void **)&adev->mes.ucode_fw_ptr[pipe]);
        fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
 
        r = amdgpu_bo_create_reserved(adev, fw_size,
-                                     64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
+                                     64 * 1024,
+                                     AMDGPU_GEM_DOMAIN_VRAM |
+                                     AMDGPU_GEM_DOMAIN_GTT,
                                      &adev->mes.data_fw_obj[pipe],
                                      &adev->mes.data_fw_gpu_addr[pipe],
                                      (void **)&adev->mes.data_fw_ptr[pipe]);
 
         * TODO: Move this into GART.
         */
        r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE,
-                                   AMDGPU_GEM_DOMAIN_VRAM, &adev->dm.dmub_bo,
+                                   AMDGPU_GEM_DOMAIN_VRAM |
+                                   AMDGPU_GEM_DOMAIN_GTT,
+                                   &adev->dm.dmub_bo,
                                    &adev->dm.dmub_bo_gpu_addr,
                                    &adev->dm.dmub_bo_cpu_addr);
        if (r)
 
 
        /* allocate space for watermarks table */
        r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
-                       sizeof(Watermarks_t),
-                       PAGE_SIZE,
-                       AMDGPU_GEM_DOMAIN_VRAM,
+                       sizeof(Watermarks_t), PAGE_SIZE,
+                       AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT,
                        &priv->smu_tables.entry[SMU10_WMTABLE].handle,
                        &priv->smu_tables.entry[SMU10_WMTABLE].mc_addr,
                        &priv->smu_tables.entry[SMU10_WMTABLE].table);
 
        /* allocate space for watermarks table */
        r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
-                       sizeof(DpmClocks_t),
-                       PAGE_SIZE,
-                       AMDGPU_GEM_DOMAIN_VRAM,
+                       sizeof(DpmClocks_t), PAGE_SIZE,
+                       AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT,
                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].handle,
                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].mc_addr,
                        &priv->smu_tables.entry[SMU10_CLOCKTABLE].table);