soundwire: amd: set ACP_PME_EN during runtime suspend sequence

Set ACP_PME_EN to 1 during runtime suspend sequence as per design flow
for ACP7.0 & ACP7.1 platforms.

Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20250207065841.4718-6-Vijendar.Mukunda@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/soundwire/amd_manager.c b/drivers/soundwire/amd_manager.c
index 50d7b10b0581583662d57a2cc0542549efc13571..0fce876dcb4216df2a7785490bcf05e269f4655a 100644 (file)
--- a/drivers/soundwire/amd_manager.c
+++ b/drivers/soundwire/amd_manager.c
@@ -1211,6 +1211,7 @@ static int __maybe_unused amd_suspend_runtime(struct device *dev)
        struct amd_sdw_manager *amd_manager = dev_get_drvdata(dev);
        struct sdw_bus *bus = &amd_manager->bus;
        int ret;
+       u32 val;
 
        if (bus->prop.hw_disabled) {
                dev_dbg(bus->dev, "SoundWire manager %d is disabled,\n",
@@ -1235,6 +1236,14 @@ static int __maybe_unused amd_suspend_runtime(struct device *dev)
                ret = amd_sdw_set_device_state(amd_manager, AMD_SDW_DEVICE_STATE_D3);
                if (ret)
                        return ret;
+               if (amd_manager->wake_en_mask) {
+                       val = readl(amd_manager->acp_mmio + ACP_PME_EN);
+                       if (!val) {
+                               writel(1, amd_manager->acp_mmio + ACP_PME_EN);
+                               val = readl(amd_manager->acp_mmio + ACP_PME_EN);
+                               dev_dbg(amd_manager->dev, "ACP_PME_EN:0x%x\n", val);
+                       }
+               }
        }
        return 0;
 }

diff --git a/drivers/soundwire/amd_manager.h b/drivers/soundwire/amd_manager.h
index 8430f279d88e9003de79708bbdd2ba7431a8c76a..1d5e94371f813e67089b25cdb87400666233e37b 100644 (file)
--- a/drivers/soundwire/amd_manager.h
+++ b/drivers/soundwire/amd_manager.h
@@ -199,6 +199,7 @@
 #define AMD_SDW1_DEVICE_STATE_MASK                     GENMASK(3, 2)
 #define AMD_SDW_DEVICE_STATE_D0                                0
 #define AMD_SDW_DEVICE_STATE_D3                                3
+#define ACP_PME_EN                                     0x0001400
 
 static u32 amd_sdw_freq_tbl[AMD_SDW_MAX_FREQ_NUM] = {
        AMD_SDW_DEFAULT_CLK_FREQ,