clk: qcom: clk-alpha-pll: Use common names for defines

The PLL run and standby modes are similar across the PLLs, thus rename
them to common names and update the use of these.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20200224045003.3783838-2-vkoul@kernel.org
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tested-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 6d946770a80fc505e90a6c649948b1f71029b6de..0bdf6e45fac9fdf5f335a97ba9f4d63da8f6f3bb 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -134,15 +134,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define PLL_HUAYRA_N_MASK              0xff
 #define PLL_HUAYRA_ALPHA_WIDTH         16
 
-#define FABIA_OPMODE_STANDBY   0x0
-#define FABIA_OPMODE_RUN       0x1
-
-#define FABIA_PLL_OUT_MASK     0x7
-#define FABIA_PLL_RATE_MARGIN  500
-
-#define TRION_PLL_STANDBY      0x0
-#define TRION_PLL_RUN          0x1
-#define TRION_PLL_OUT_MASK     0x7
+#define PLL_STANDBY            0x0
+#define PLL_RUN                        0x1
+#define PLL_OUT_MASK           0x7
+#define PLL_RATE_MARGIN                500
 
 #define pll_alpha_width(p)                                     \
                ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
@@ -766,7 +761,7 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
        if (ret)
                return 0;
 
-       return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
+       return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
 }
 
 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
@@ -796,7 +791,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
        }
 
        /* Set operation mode to RUN */
-       regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
+       regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
 
        ret = wait_for_pll_enable_lock(pll);
        if (ret)
@@ -804,7 +799,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
 
        /* Enable the PLL outputs */
        ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
-                                TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
+                                PLL_OUT_MASK, PLL_OUT_MASK);
        if (ret)
                return ret;
 
@@ -837,12 +832,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
 
        /* Disable the PLL outputs */
        ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
-                                TRION_PLL_OUT_MASK, 0);
+                                PLL_OUT_MASK, 0);
        if (ret)
                return;
 
        /* Place the PLL mode in STANDBY */
-       regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
+       regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
        regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
 }
 
@@ -1089,14 +1084,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
                return ret;
 
        /* Skip If PLL is already running */
-       if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
+       if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
                return 0;
 
        ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
        if (ret)
                return ret;
 
-       ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+       ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
        if (ret)
                return ret;
 
@@ -1105,7 +1100,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
        if (ret)
                return ret;
 
-       ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
+       ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
        if (ret)
                return ret;
 
@@ -1114,7 +1109,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
                return ret;
 
        ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
-                                FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
+                                PLL_OUT_MASK, PLL_OUT_MASK);
        if (ret)
                return ret;
 
@@ -1144,13 +1139,12 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
                return;
 
        /* Disable main outputs */
-       ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
-                                0);
+       ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
        if (ret)
                return;
 
        /* Place the PLL in STANDBY */
-       regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+       regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
 }
 
 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
@@ -1171,7 +1165,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
        u32 l, alpha_width = pll_alpha_width(pll);
        u64 a;
-       unsigned long rrate, max = rate + FABIA_PLL_RATE_MARGIN;
+       unsigned long rrate, max = rate + PLL_RATE_MARGIN;
 
        rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
 
@@ -1230,7 +1224,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
         * Due to a limited number of bits for fractional rate programming, the
         * rounded up rate could be marginally higher than the requested rate.
         */
-       if (rrate > (cal_freq + FABIA_PLL_RATE_MARGIN) || rrate < cal_freq)
+       if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
                return -EINVAL;
 
        /* Setup PLL for calibration frequency */