lp->options = XAE_OPTION_DEFAULTS;
        lp->rx_bd_num = RX_BD_NUM_DEFAULT;
        lp->tx_bd_num = TX_BD_NUM_DEFAULT;
+
+       lp->clk = devm_clk_get_optional(&pdev->dev, NULL);
+       if (IS_ERR(lp->clk)) {
+               ret = PTR_ERR(lp->clk);
+               goto free_netdev;
+       }
+       ret = clk_prepare_enable(lp->clk);
+       if (ret) {
+               dev_err(&pdev->dev, "Unable to enable clock: %d\n", ret);
+               goto free_netdev;
+       }
+
        /* Map device registers */
        ethres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        lp->regs = devm_ioremap_resource(&pdev->dev, ethres);
 
        lp->phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
        if (lp->phy_node) {
-               lp->clk = devm_clk_get(&pdev->dev, NULL);
-               if (IS_ERR(lp->clk)) {
-                       dev_warn(&pdev->dev, "Failed to get clock: %ld\n",
-                                PTR_ERR(lp->clk));
-                       lp->clk = NULL;
-               } else {
-                       ret = clk_prepare_enable(lp->clk);
-                       if (ret) {
-                               dev_err(&pdev->dev, "Unable to enable clock: %d\n",
-                                       ret);
-                               goto free_netdev;
-                       }
-               }
-
                ret = axienet_mdio_setup(lp);
                if (ret)
                        dev_warn(&pdev->dev,