drm/xe/guc: Port Wa_14012197797/Wa_22011391025 to xe_wa

Wa_14012197797 and Wa_22011391025 apply to DG2 using the same action.
They apply to slightly different conditions. Add both to the oob rules
so they are both reported as active.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230526164358.86393-16-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 1b3fbbd749236596bba31fa6b35c9281daa0ffd2..54aaf6e6b5777413ba4fba8387a245904fe50063 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -147,14 +147,7 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
            xe->info.platform == XE_DG2)
                flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
-       /*
-        * Wa_14012197797
-        * Wa_22011391025
-        *
-        * The same WA bit is used for both and 22011391025 is applicable to
-        * all DG2.
-        */
-       if (xe->info.platform == XE_DG2)
+       if (XE_WA(gt, 22011391025) || XE_WA(gt, 14012197797))
                flags |= GUC_WA_DUAL_QUEUE;
 
        /*

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 9b29a0dd09341b58ed4888351dff7ee5ae0ace9c..77ac4a4a3296cbeb884094338d8666036bfb6fd2 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -1,2 +1,4 @@
 22012773006    GRAPHICS_VERSION_RANGE(1200, 1250)
 16011759253    SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)
+22011391025    PLATFORM(DG2)
+14012197797    PLATFORM(DG2), GRAPHICS_STEP(A0, B0)