MIPS: Ingenic: Fix bugs when detecting X1000's L2 cache.

1.fix bugs when detecting L2 cache sets value.
2.fix bugs when detecting L2 cache ways value.

Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: ralf@linux-mips.org
Cc: paul@crapouillou.net
Cc: jhogan@kernel.org
Cc: malat@debian.org
Cc: gregkh@linuxfoundation.org
Cc: tglx@linutronix.de
Cc: allison@lohutok.net
Cc: syq@debian.org
Cc: chenhc@lemote.com
Cc: jiaxun.yang@flygoat.com

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 9385ddbd6e4794b865759402b4b25def71c40cc6..dbdbfe5d84086bab11b9ecf108474db0c2f307d6 100644 (file)
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -221,13 +221,26 @@ static inline int __init mips_sc_probe(void)
        else
                return 0;
 
-       /*
-        * According to config2 it would be 5-ways, but that is contradicted
-        * by all documentation.
-        */
-       if (current_cpu_type() == CPU_XBURST &&
-                               mips_machtype == MACH_INGENIC_JZ4770)
-               c->scache.ways = 4;
+       if (current_cpu_type() == CPU_XBURST) {
+               switch (mips_machtype) {
+               /*
+                * According to config2 it would be 5-ways, but that is
+                * contradicted by all documentation.
+                */
+               case MACH_INGENIC_JZ4770:
+                       c->scache.ways = 4;
+                       break;
+
+               /*
+                * According to config2 it would be 5-ways and 512-sets,
+                * but that is contradicted by all documentation.
+                */
+               case MACH_INGENIC_X1000:
+                       c->scache.sets = 256;
+                       c->scache.ways = 4;
+                       break;
+               }
+       }
 
        c->scache.waysize = c->scache.sets * c->scache.linesz;
        c->scache.waybit = __ffs(c->scache.waysize);