int irq;
        struct irq_domain *domain;
        struct gpio_chip gc;
+       struct device *dev;
        enum mxs_gpio_id devid;
        u32 both_edges;
 };
 {
        struct irq_chip_generic *gc;
        struct irq_chip_type *ct;
+       int rv;
 
-       gc = irq_alloc_generic_chip("gpio-mxs", 2, irq_base,
-                                   port->base, handle_level_irq);
+       gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxs", 2, irq_base,
+                                        port->base, handle_level_irq);
        if (!gc)
                return -ENOMEM;
 
        ct->regs.disable = PINCTRL_IRQEN(port) + MXS_CLR;
        ct->handler = handle_level_irq;
 
-       irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
-                              IRQ_NOREQUEST, 0);
+       rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
+                                        IRQ_GC_INIT_NESTED_LOCK,
+                                        IRQ_NOREQUEST, 0);
 
-       return 0;
+       return rv;
 }
 
 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
        if (port->id < 0)
                return port->id;
        port->devid = (enum mxs_gpio_id) of_id->data;
+       port->dev = &pdev->dev;
        port->irq = platform_get_irq(pdev, 0);
        if (port->irq < 0)
                return port->irq;