#define portaddrl(port, reg) \
        ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 
-#define rd_reg(port, reg) (readb_relaxed(portaddr(port, reg)))
+static u32 rd_reg(struct uart_port *port, u32 reg)
+{
+       switch (port->iotype) {
+       case UPIO_MEM:
+               return readb_relaxed(portaddr(port, reg));
+       case UPIO_MEM32:
+               return readl_relaxed(portaddr(port, reg));
+       default:
+               return 0;
+       }
+       return 0;
+}
+
 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 
-#define wr_reg(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
+static void wr_reg(struct uart_port *port, u32 reg, u32 val)
+{
+       switch (port->iotype) {
+       case UPIO_MEM:
+               writeb_relaxed(val, portaddr(port, reg));
+               break;
+       case UPIO_MEM32:
+               writel_relaxed(val, portaddr(port, reg));
+               break;
+       }
+}
+
 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 
 /* Byte-order aware bit setting/clearing functions. */
        struct device_node *np = pdev->dev.of_node;
        struct s3c24xx_uart_port *ourport;
        int index = probe_index;
-       int ret;
+       int ret, prop = 0;
 
        if (np) {
                ret = of_alias_get_id(np, "serial");
                        dev_get_platdata(&pdev->dev) :
                        ourport->drv_data->def_cfg;
 
-       if (np)
+       if (np) {
                of_property_read_u32(np,
                        "samsung,uart-fifosize", &ourport->port.fifosize);
 
+               if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
+                       switch (prop) {
+                       case 1:
+                               ourport->port.iotype = UPIO_MEM;
+                               break;
+                       case 4:
+                               ourport->port.iotype = UPIO_MEM32;
+                               break;
+                       default:
+                               dev_warn(&pdev->dev, "unsupported reg-io-width (%d)\n",
+                                               prop);
+                               ret = -EINVAL;
+                               break;
+                       }
+               }
+       }
+
        if (ourport->drv_data->fifosize[index])
                ourport->port.fifosize = ourport->drv_data->fifosize[index];
        else if (ourport->info->fifosize)
  * Early console.
  */
 
+static void wr_reg_barrier(struct uart_port *port, u32 reg, u32 val)
+{
+       switch (port->iotype) {
+       case UPIO_MEM:
+               writeb(val, portaddr(port, reg));
+               break;
+       case UPIO_MEM32:
+               writel(val, portaddr(port, reg));
+               break;
+       }
+}
+
 struct samsung_early_console_data {
        u32 txfull_mask;
 };
        else
                samsung_early_busyuart(port);
 
-       writeb(c, port->membase + S3C2410_UTXH);
+       wr_reg_barrier(port, S3C2410_UTXH, c);
 }
 
 static void samsung_early_write(struct console *con, const char *s,