.address_watch_execute = kgd_gfx_v9_address_watch_execute,
        .wave_control_execute = kgd_gfx_v9_wave_control_execute,
        .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
-       .get_atc_vmid_pasid_mapping_pasid =
-                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
-       .get_atc_vmid_pasid_mapping_valid =
-                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
+       .get_atc_vmid_pasid_mapping_info =
+                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
        .get_tile_config = kgd_gfx_v9_get_tile_config,
        .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
        .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
 
                                        unsigned int watch_point_id,
                                        unsigned int reg_offset);
 
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-               uint8_t vmid);
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-               uint8_t vmid);
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid);
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
                uint64_t page_table_base);
 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
        .address_watch_execute = kgd_address_watch_execute,
        .wave_control_execute = kgd_wave_control_execute,
        .address_watch_get_offset = kgd_address_watch_get_offset,
-       .get_atc_vmid_pasid_mapping_pasid =
-                       get_atc_vmid_pasid_mapping_pasid,
-       .get_atc_vmid_pasid_mapping_valid =
-                       get_atc_vmid_pasid_mapping_valid,
+       .get_atc_vmid_pasid_mapping_info =
+                       get_atc_vmid_pasid_mapping_info,
        .get_tile_config = amdgpu_amdkfd_get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
        .invalidate_tlbs = invalidate_tlbs,
        return 0;
 }
 
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-                                                       uint8_t vmid)
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid)
 {
-       uint32_t reg;
+       uint32_t value;
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 
-       reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+       value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
                     + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
-}
-
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-                                                               uint8_t vmid)
-{
-       uint32_t reg;
-       struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+       *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 
-       reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
-                    + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+       return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 }
 
 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
        int vmid;
+       uint16_t queried_pasid;
+       bool ret;
        struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 
        if (amdgpu_emu_mode == 0 && ring->sched.ready)
        for (vmid = 0; vmid < 16; vmid++) {
                if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
                        continue;
-               if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
-                       if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
-                               == pasid) {
-                               amdgpu_gmc_flush_gpu_tlb(adev, vmid,
-                                               AMDGPU_GFXHUB_0, 0);
-                               break;
-                       }
+
+               ret = get_atc_vmid_pasid_mapping_info(kgd, vmid,
+                               &queried_pasid);
+               if (ret && queried_pasid == pasid) {
+                       amdgpu_gmc_flush_gpu_tlb(adev, vmid,
+                                       AMDGPU_GFXHUB_0, 0);
+                       break;
                }
        }
 
 
                                        unsigned int watch_point_id,
                                        unsigned int reg_offset);
 
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid);
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-                                                       uint8_t vmid);
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid);
 
 static void set_scratch_backing_va(struct kgd_dev *kgd,
                                        uint64_t va, uint32_t vmid);
        .address_watch_execute = kgd_address_watch_execute,
        .wave_control_execute = kgd_wave_control_execute,
        .address_watch_get_offset = kgd_address_watch_get_offset,
-       .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid,
-       .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid,
+       .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
        .set_scratch_backing_va = set_scratch_backing_va,
        .get_tile_config = get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
        return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset];
 }
 
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-                                                       uint8_t vmid)
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid)
 {
-       uint32_t reg;
+       uint32_t value;
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 
-       reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
-}
-
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-                                                               uint8_t vmid)
-{
-       uint32_t reg;
-       struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+       value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+       *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 
-       reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+       return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 }
 
 static void set_scratch_backing_va(struct kgd_dev *kgd,
 
                                        unsigned int watch_point_id,
                                        unsigned int reg_offset);
 
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-               uint8_t vmid);
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-               uint8_t vmid);
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid);
 static void set_scratch_backing_va(struct kgd_dev *kgd,
                                        uint64_t va, uint32_t vmid);
 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
        .address_watch_execute = kgd_address_watch_execute,
        .wave_control_execute = kgd_wave_control_execute,
        .address_watch_get_offset = kgd_address_watch_get_offset,
-       .get_atc_vmid_pasid_mapping_pasid =
-                       get_atc_vmid_pasid_mapping_pasid,
-       .get_atc_vmid_pasid_mapping_valid =
-                       get_atc_vmid_pasid_mapping_valid,
+       .get_atc_vmid_pasid_mapping_info =
+                       get_atc_vmid_pasid_mapping_info,
        .set_scratch_backing_va = set_scratch_backing_va,
        .get_tile_config = get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
        return 0;
 }
 
-static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-                                                       uint8_t vmid)
+static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid)
 {
-       uint32_t reg;
+       uint32_t value;
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 
-       reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
-}
-
-static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-                                                               uint8_t vmid)
-{
-       uint32_t reg;
-       struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+       value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
+       *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 
-       reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+       return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 }
 
 static int kgd_address_watch_disable(struct kgd_dev *kgd)
 
        return 0;
 }
 
-bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-                                                       uint8_t vmid)
+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid)
 {
-       uint32_t reg;
+       uint32_t value;
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
 
-       reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
+       value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
                     + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
-}
-
-uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-                                                               uint8_t vmid)
-{
-       uint32_t reg;
-       struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
+       *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 
-       reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
-                    + vmid);
-       return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK;
+       return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 }
 
 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid,
 {
        struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
        int vmid, i;
+       uint16_t queried_pasid;
+       bool ret;
        struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
        uint32_t flush_type = 0;
 
        for (vmid = 0; vmid < 16; vmid++) {
                if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid))
                        continue;
-               if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {
-                       if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid)
-                               == pasid) {
-                               for (i = 0; i < adev->num_vmhubs; i++)
-                                       amdgpu_gmc_flush_gpu_tlb(adev, vmid,
-                                                               i, flush_type);
-                               break;
-                       }
+
+               ret = kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(kgd, vmid,
+                               &queried_pasid);
+               if (ret && queried_pasid == pasid) {
+                       for (i = 0; i < adev->num_vmhubs; i++)
+                               amdgpu_gmc_flush_gpu_tlb(adev, vmid,
+                                                       i, flush_type);
+                       break;
                }
        }
 
        .address_watch_execute = kgd_gfx_v9_address_watch_execute,
        .wave_control_execute = kgd_gfx_v9_wave_control_execute,
        .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
-       .get_atc_vmid_pasid_mapping_pasid =
-                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid,
-       .get_atc_vmid_pasid_mapping_valid =
-                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid,
+       .get_atc_vmid_pasid_mapping_info =
+                       kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
        .get_tile_config = kgd_gfx_v9_get_tile_config,
        .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
        .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs,
 
                                        unsigned int watch_point_id,
                                        unsigned int reg_offset);
 
-bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
-               uint8_t vmid);
-uint16_t kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
-               uint8_t vmid);
+bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
+                                       uint8_t vmid, uint16_t *p_pasid);
 void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid,
                uint64_t page_table_base);
 int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid);
 
        const struct cik_ih_ring_entry *ihre =
                        (const struct cik_ih_ring_entry *)ih_ring_entry;
        const struct kfd2kgd_calls *f2g = dev->kfd2kgd;
-       unsigned int vmid, pasid;
+       unsigned int vmid;
+       uint16_t pasid;
+       bool ret;
 
        /* This workaround is due to HW/FW limitation on Hawaii that
         * VMID and PASID are not written into ih_ring_entry
                *tmp_ihre = *ihre;
 
                vmid = f2g->read_vmid_from_vmfault_reg(dev->kgd);
-               pasid = f2g->get_atc_vmid_pasid_mapping_pasid(dev->kgd, vmid);
+               ret = f2g->get_atc_vmid_pasid_mapping_info(dev->kgd, vmid, &pasid);
 
                tmp_ihre->ring_id &= 0x000000ff;
                tmp_ihre->ring_id |= vmid << 8;
                tmp_ihre->ring_id |= pasid << 16;
 
-               return (pasid != 0) &&
+               return ret && (pasid != 0) &&
                        vmid >= dev->vm_info.first_vmid_kfd &&
                        vmid <= dev->vm_info.last_vmid_kfd;
        }
 
 {
        int status = 0;
        unsigned int vmid;
+       uint16_t queried_pasid;
        union SQ_CMD_BITS reg_sq_cmd;
        union GRBM_GFX_INDEX_BITS reg_gfx_index;
        struct kfd_process_device *pdd;
         */
 
        for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {
-               if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid
-                               (dev->kgd, vmid)) {
-                       if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_pasid
-                                       (dev->kgd, vmid) == p->pasid) {
-                               pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
-                                               vmid, p->pasid);
-                               break;
-                       }
+               status = dev->kfd2kgd->get_atc_vmid_pasid_mapping_info
+                               (dev->kgd, vmid, &queried_pasid);
+
+               if (status && queried_pasid == p->pasid) {
+                       pr_debug("Killing wave fronts of vmid %d and pasid 0x%x\n",
+                                       vmid, p->pasid);
+                       break;
                }
        }
 
 
        uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
                                        unsigned int watch_point_id,
                                        unsigned int reg_offset);
-       bool (*get_atc_vmid_pasid_mapping_valid)(
+       bool (*get_atc_vmid_pasid_mapping_info)(
                                        struct kgd_dev *kgd,
-                                       uint8_t vmid);
-       uint16_t (*get_atc_vmid_pasid_mapping_pasid)(
-                                       struct kgd_dev *kgd,
-                                       uint8_t vmid);
+                                       uint8_t vmid,
+                                       uint16_t *p_pasid);
 
        /* No longer needed from GFXv9 onward. The scratch base address is
         * passed to the shader by the CP. It's the user mode driver's