perf/x86/amd/core: Detect available counters

If AMD Performance Monitoring Version 2 (PerfMonV2) is
supported, use CPUID leaf 0x80000022 EBX to detect the
number of Core PMCs. This offers more flexibility if the
counts change in later processor families.

Signed-off-by: Sandipan Das <sandipan.das@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/68a6d9688df189267db26530378870edd34f7b06.1650515382.git.sandipan.das@amd.com

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index b70dfa028ba58b05654f7c68f288b4c6598e6ca9..52fd7941a7248f79f0e4f8ca9b375a76de2dfcf8 100644 (file)
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -1186,6 +1186,7 @@ static const struct attribute_group *amd_attr_update[] = {
 
 static int __init amd_core_pmu_init(void)
 {
+       union cpuid_0x80000022_ebx ebx;
        u64 even_ctr_mask = 0ULL;
        int i;
 
@@ -1206,9 +1207,14 @@ static int __init amd_core_pmu_init(void)
 
        /* Check for Performance Monitoring v2 support */
        if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) {
+               ebx.full = cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES);
+
                /* Update PMU version for later usage */
                x86_pmu.version = 2;
 
+               /* Find the number of available Core PMCs */
+               x86_pmu.num_counters = ebx.split.num_core_pmc;
+
                amd_pmu_global_cntr_mask = (1ULL << x86_pmu.num_counters) - 1;
        }
 

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 8199fc5a37eae2d4a1db4636f8c9cdd3b4232998..c6cc07f46556ba402b98bfe1d62dd45606840a20 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -186,6 +186,18 @@ union cpuid28_ecx {
        unsigned int            full;
 };
 
+/*
+ * AMD "Extended Performance Monitoring and Debug" CPUID
+ * detection/enumeration details:
+ */
+union cpuid_0x80000022_ebx {
+       struct {
+               /* Number of Core Performance Counters */
+               unsigned int    num_core_pmc:4;
+       } split;
+       unsigned int            full;
+};
+
 struct x86_pmu_capability {
        int             version;
        int             num_counters_gp;
@@ -367,6 +379,11 @@ struct pebs_xmm {
        u64 xmm[16*2];  /* two entries for each register */
 };
 
+/*
+ * AMD Extended Performance Monitoring and Debug cpuid feature detection
+ */
+#define EXT_PERFMON_DEBUG_FEATURES             0x80000022
+
 /*
  * IBS cpuid feature detection
  */