drm/i915/gvt: rename F_IN_CTX flag to F_SR_IN_CTX

F_IN_CTX is an inaccurate flag name, because people may wrongly think all
MMIOs in context image are with this flag. But actually, this flag is only
for MMIOs both in GVT's save-restore list and in hardare logical
context's image.

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Yan Zhao <yan.y.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200811060944.3039-1-yan.y.zhao@intel.com

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index f1940939260aaa401f5dba6174d463203d9a179c..018509eeb0fe2721e84b56464c48ebcc08511b81 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -976,7 +976,7 @@ static int cmd_reg_handler(struct parser_exec_state *s,
         * inhibit context will restore with correct values
         */
        if (IS_GEN(s->engine->i915, 9) &&
-           intel_gvt_mmio_is_in_ctx(gvt, offset) &&
+           intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
            !strncmp(cmd, "lri", 3)) {
                intel_gvt_hypervisor_read_gpa(s->vgpu,
                        s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index a4a6db6b7f9087c96be422b73a2e9f2f542ca6db..899945b91cc6b44691d206ea87fed765efcce94a 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -256,8 +256,10 @@ struct intel_gvt_mmio {
 #define F_CMD_ACCESSED (1 << 5)
 /* This reg could be accessed by unaligned address */
 #define F_UNALIGN      (1 << 6)
-/* This reg is saved/restored in context */
-#define F_IN_CTX       (1 << 7)
+/* This reg is in GVT's mmio save-restor list and in hardware
+ * logical context image
+ */
+#define F_SR_IN_CTX    (1 << 7)
 
        struct gvt_mmio_block *mmio_block;
        unsigned int num_mmio_block;
@@ -645,30 +647,33 @@ static inline bool intel_gvt_mmio_has_mode_mask(
 }
 
 /**
- * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask
+ * intel_gvt_mmio_is_sr_in_ctx -
+ *             check if an MMIO has F_SR_IN_CTX mask
  * @gvt: a GVT device
  * @offset: register offset
  *
  * Returns:
- * True if a MMIO has a in-context mask, false if it isn't.
+ * True if an MMIO has an F_SR_IN_CTX  mask, false if it isn't.
  *
  */
-static inline bool intel_gvt_mmio_is_in_ctx(
+static inline bool intel_gvt_mmio_is_sr_in_ctx(
                        struct intel_gvt *gvt, unsigned int offset)
 {
-       return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX;
+       return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;
 }
 
 /**
- * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context
+ * intel_gvt_mmio_set_sr_in_ctx -
+ *             mask an MMIO in GVT's mmio save-restore list and also
+ *             in hardware logical context image
  * @gvt: a GVT device
  * @offset: register offset
  *
  */
-static inline void intel_gvt_mmio_set_in_ctx(
+static inline void intel_gvt_mmio_set_sr_in_ctx(
                        struct intel_gvt *gvt, unsigned int offset)
 {
-       gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX;
+       gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;
 }
 
 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu);

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 86a60bdf0818cfe55053d49ad177602ad785c490..afe574d6b3b52073c6bea40c4976898726da93a2 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -595,7 +595,7 @@ void intel_gvt_init_engine_mmio_context(struct intel_gvt *gvt)
             i915_mmio_reg_valid(mmio->reg); mmio++) {
                if (mmio->in_context) {
                        gvt->engine_mmio_list.ctx_mmio_count[mmio->id]++;
-                       intel_gvt_mmio_set_in_ctx(gvt, mmio->reg.reg);
+                       intel_gvt_mmio_set_sr_in_ctx(gvt, mmio->reg.reg);
                }
        }
 }