drm/i915: Check for FIFO underruns at the end of modeset on gmch

FIFO underruns don't generate interrupts on gmch platforms, so
if we want to know whether a modeset triggered FIFO underruns we
need to explicitly check for them.

As a modeset on one pipe could cause underruns on other pipes,
check for underruns on all pipes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Thomas Wood <thomas.wood@intel.com>
[danvet: Fix up merge error, kudos to Ville for noticing it.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 83ad4b43bcd660ab91b4237c5e840bb1c0f55768..57e86bae8f01209ac43c5a055127e3c89790bb3a 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -306,6 +306,34 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev)
        return true;
 }
 
+void i9xx_check_fifo_underruns(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+       struct intel_crtc *crtc;
+       unsigned long flags;
+
+       spin_lock_irqsave(&dev_priv->irq_lock, flags);
+
+       for_each_intel_crtc(dev, crtc) {
+               u32 reg = PIPESTAT(crtc->pipe);
+               u32 pipestat;
+
+               if (crtc->cpu_fifo_underrun_disabled)
+                       continue;
+
+               pipestat = I915_READ(reg) & 0xffff0000;
+               if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
+                       continue;
+
+               I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
+               POSTING_READ(reg);
+
+               DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
+       }
+
+       spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
+}
+
 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
                                             enum pipe pipe, bool enable)
 {

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6c5db7c8caf42ee9c7e8f1a088307359901b347a..8d960d240611c1cfeeeaee87e743be8e8e692c8c 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4625,6 +4625,9 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
        intel_crtc_enable_planes(crtc);
 
        drm_crtc_vblank_on(crtc);
+
+       /* Underruns don't raise interrupts, so check manually. */
+       i9xx_check_fifo_underruns(dev);
 }
 
 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
@@ -4704,6 +4707,9 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
        intel_crtc_enable_planes(crtc);
 
        drm_crtc_vblank_on(crtc);
+
+       /* Underruns don't raise interrupts, so check manually. */
+       i9xx_check_fifo_underruns(dev);
 }
 
 static void i9xx_pfit_disable(struct intel_crtc *crtc)

diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a78eb75411c9f04f16dce29c04cc90e09d9995ae..fe2533ba52a9d78a03a6d2f775421acff87326a6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -680,6 +680,7 @@ void bdw_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void intel_runtime_pm_disable_interrupts(struct drm_device *dev);
 void intel_runtime_pm_restore_interrupts(struct drm_device *dev);
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
+void i9xx_check_fifo_underruns(struct drm_device *dev);
 
 
 /* intel_crt.c */