drm/amd/display: update dml input population function

Update dcn20_populate_dml_pipes_from_context to correctly handle odm
when no surface is provided.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 080d4581a93db2aa3b03913c21914f3e1cd00ecb..883ecd2ed4c8d00f1141ae7b7b8457019b3f9155 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1949,9 +1949,14 @@ int dcn20_populate_dml_pipes_from_context(
                }
                pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
                if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
-                               == res_ctx->pipe_ctx[i].plane_state)
-                       pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
-               else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
+                               == res_ctx->pipe_ctx[i].plane_state) {
+                       struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
+
+                       while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
+                                       == res_ctx->pipe_ctx[i].plane_state)
+                               first_pipe = first_pipe->top_pipe;
+                       pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
+               } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
                        struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
 
                        while (first_pipe->prev_odm_pipe)
@@ -2046,6 +2051,7 @@ int dcn20_populate_dml_pipes_from_context(
                pipes[pipe_cnt].pipe.src.cur1_bpp = dm_cur_32bit;
 
                if (!res_ctx->pipe_ctx[i].plane_state) {
+                       pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
                        pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
                        pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
                        pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
@@ -2071,19 +2077,21 @@ int dcn20_populate_dml_pipes_from_context(
                        pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
                        pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
                        pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
-                       pipes[pipe_cnt].pipe.src.is_hsplit = 0;
-                       pipes[pipe_cnt].pipe.dest.odm_combine = 0;
                        pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
                        pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
+
+                       if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
+                               pipes[pipe_cnt].pipe.src.viewport_width /= 2;
+                               pipes[pipe_cnt].pipe.dest.recout_width /= 2;
+                       }
                } else {
                        struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
                        struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
 
                        pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
-                       pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe
-                                       && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
-                                       || (res_ctx->pipe_ctx[i].top_pipe
-                                       && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln);
+                       pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
+                                       || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
+                                       || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
                        pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
                                        || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
                        pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index 9bb8bff4cdd99ac4d430f74d1c326025103b82de..35fe3c640330472874f5bacb0c3eb78d1c003343 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -112,6 +112,7 @@ struct _vcs_dpi_soc_bounding_box_st {
        int use_urgent_burst_bw;
        unsigned int num_states;
        struct _vcs_dpi_voltage_scaling_st clock_limits[MAX_CLOCK_LIMIT_STATES];
+       double min_dcfclk;
        bool do_urgent_latency_adjustment;
        double urgent_latency_adjustment_fabric_clock_component_us;
        double urgent_latency_adjustment_fabric_clock_reference_mhz;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index b3c96d9b472f043321afe0ec082192499e12c271..e23fa0f05f06192c39a8b2f2bb4b0db9e50bc82b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -266,8 +266,6 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
                mode_lib->vba.MaxDispclk[i] = soc->clock_limits[i].dispclk_mhz;
                mode_lib->vba.DTBCLKPerState[i] = soc->clock_limits[i].dtbclk_mhz;
        }
-       mode_lib->vba.MinVoltageLevel = 0;
-       mode_lib->vba.MaxVoltageLevel = mode_lib->vba.soc.num_states;
 
        mode_lib->vba.DoUrgentLatencyAdjustment =
                soc->do_urgent_latency_adjustment;

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 2875efd854673fa7fbbe2b3a21aaeecece1f010d..cb563a429590f2bb20faa01b9cb2eb34c8839944 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -842,8 +842,6 @@ struct vba_vars_st {
        double DCCRateChroma[DC__NUM_DPP__MAX];
 
        double PHYCLKD18PerState[DC__VOLTAGE_STATES + 1];
-       int MinVoltageLevel;
-       int MaxVoltageLevel;
 
        bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
        bool NumberOfHDMIFRLSupport;
@@ -880,7 +878,6 @@ struct vba_vars_st {
        double TotalMetaRowBandwidth[DC__VOLTAGE_STATES + 1][2];
        double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES + 1][2];
        double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES + 1][2];
-       bool UseMinimumRequiredDCFCLK;
        double WritebackDelayTime[DC__NUM_DPP__MAX];
        unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
        unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];