list_splice_tail(trim_list, &vres->blocks);
        }
 
-       list_for_each_entry(block, &vres->blocks, link)
-               vis_usage += amdgpu_vram_mgr_vis_size(adev, block);
+       vres->base.start = 0;
+       list_for_each_entry(block, &vres->blocks, link) {
+               unsigned long start;
 
-       block = amdgpu_vram_mgr_first_block(&vres->blocks);
-       if (!block) {
-               r = -EINVAL;
-               goto error_fini;
-       }
+               start = amdgpu_vram_mgr_block_start(block) +
+                       amdgpu_vram_mgr_block_size(block);
+               start >>= PAGE_SHIFT;
 
-       vres->base.start = amdgpu_vram_mgr_block_start(block) >> PAGE_SHIFT;
+               if (start > vres->base.num_pages)
+                       start -= vres->base.num_pages;
+               else
+                       start = 0;
+               vres->base.start = max(vres->base.start, start);
+
+               vis_usage += amdgpu_vram_mgr_vis_size(adev, block);
+       }
 
        if (amdgpu_is_vram_mgr_blocks_contiguous(&vres->blocks))
                vres->base.placement |= TTM_PL_FLAG_CONTIGUOUS;