xtensa: add XTFPGA DTS

Add common XTFPGA parts as *.dtsi (base board, flash) and DTS for LX60
and for ML605.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

diff --git a/arch/xtensa/boot/dts/lx60.dts b/arch/xtensa/boot/dts/lx60.dts
new file mode 100644 (file)
index 0000000..2eab365
--- /dev/null
+++ b/arch/xtensa/boot/dts/lx60.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-4m.dtsi"
+
+/ {
+       compatible = "xtensa,lx60";
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x04000000>;
+       };
+};

diff --git a/arch/xtensa/boot/dts/ml605.dts b/arch/xtensa/boot/dts/ml605.dts
new file mode 100644 (file)
index 0000000..6ed51d6
--- /dev/null
+++ b/arch/xtensa/boot/dts/ml605.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/include/ "xtfpga.dtsi"
+/include/ "xtfpga-flash-16m.dtsi"
+
+/ {
+       compatible = "xtensa,ml605";
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x08000000>;
+       };
+};

diff --git a/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi b/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi
new file mode 100644 (file)
index 0000000..e5703c7
--- /dev/null
+++ b/arch/xtensa/boot/dts/xtfpga-flash-16m.dtsi
@@ -0,0 +1,26 @@
+/ {
+       flash: flash@f8000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0xf8000000 0x01000000>;
+               bank-width = <2>;
+               device-width = <2>;
+               partition@0x0 {
+                       label = "boot loader area";
+                       reg = <0x00000000 0x00400000>;
+               };
+               partition@0x400000 {
+                       label = "kernel image";
+                       reg = <0x00400000 0x00600000>;
+               };
+               partition@0xa00000 {
+                       label = "data";
+                       reg = <0x00a00000 0x005e0000>;
+               };
+               partition@0xfe0000 {
+                       label = "boot environment";
+                       reg = <0x00fe0000 0x00020000>;
+               };
+        };
+};

diff --git a/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi b/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi
new file mode 100644 (file)
index 0000000..6f9c10d
--- /dev/null
+++ b/arch/xtensa/boot/dts/xtfpga-flash-4m.dtsi
@@ -0,0 +1,18 @@
+/ {
+       flash: flash@f8000000 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "cfi-flash";
+               reg = <0xf8000000 0x00400000>;
+               bank-width = <2>;
+               device-width = <2>;
+               partition@0x0 {
+                       label = "boot loader area";
+                       reg = <0x00000000 0x003f0000>;
+               };
+               partition@0x3f0000 {
+                       label = "boot environment";
+                       reg = <0x003f0000 0x00010000>;
+               };
+        };
+};

diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi
new file mode 100644 (file)
index 0000000..7eda6ec
--- /dev/null
+++ b/arch/xtensa/boot/dts/xtfpga.dtsi
@@ -0,0 +1,56 @@
+/ {
+       compatible = "xtensa,xtfpga";
+       #address-cells = <1>;
+       #size-cells = <1>;
+       interrupt-parent = <&pic>;
+
+       chosen {
+               bootargs = "earlycon=uart8250,mmio32,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x00000000 0x06000000>;
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu@0 {
+                       compatible = "xtensa,cpu";
+                       reg = <0>;
+                       /* Filled in by platform_setup from FPGA register
+                        * clock-frequency = <100000000>;
+                        */
+               };
+       };
+
+       pic: pic {
+               compatible = "xtensa,pic";
+               /* one cell: internal irq number,
+                * two cells: second cell == 0: internal irq number
+                *            second cell == 1: external irq number
+                */
+               #interrupt-cells = <2>;
+               interrupt-controller;
+       };
+
+       serial0: serial@fd050020 {
+               device_type = "serial";
+               compatible = "ns16550a";
+               no-loopback-test;
+               reg = <0xfd050020 0x20>;
+               reg-shift = <2>;
+               interrupts = <0 1>; /* external irq 0 */
+               /* Filled in by platform_setup from FPGA register
+                * clock-frequency = <100000000>;
+                */
+       };
+
+       enet0: ethoc@fd030000 {
+               compatible = "opencores,ethoc";
+               reg = <0xfd030000 0x4000 0xfd800000 0x4000>;
+               interrupts = <1 1>; /* external irq 1 */
+               local-mac-address = [00 50 c2 13 6f 00];
+       };
+};