static const struct regmap_range axp20x_writeable_ranges[] = {
        regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE),
        regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES),
+       regmap_reg_range(AXP20X_RDC_H, AXP20X_OCV(AXP20X_OCV_MAX)),
 };
 
 static const struct regmap_range axp20x_volatile_ranges[] = {
+       regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP20X_USB_OTG_STATUS),
+       regmap_reg_range(AXP20X_CHRG_CTRL1, AXP20X_CHRG_CTRL2),
        regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
+       regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
+       regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
+       regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
 };
 
 static const struct regmap_access_table axp20x_writeable_table = {
        .val_bits       = 8,
        .wr_table       = &axp20x_writeable_table,
        .volatile_table = &axp20x_volatile_table,
-       .max_register   = AXP20X_FG_RES,
+       .max_register   = AXP20X_OCV(AXP20X_OCV_MAX),
        .cache_type     = REGCACHE_RBTREE,
 };
 
 
 #define AXP20X_CC_CTRL                 0xb8
 #define AXP20X_FG_RES                  0xb9
 
+/* OCV */
+#define AXP20X_RDC_H                   0xba
+#define AXP20X_RDC_L                   0xbb
+#define AXP20X_OCV(m)                  (0xc0 + (m))
+#define AXP20X_OCV_MAX                 0xf
+
 /* AXP22X specific registers */
 #define AXP22X_BATLOW_THRES1           0xe6