soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets

Dessert the PHY reset when powering up the domain and put it back
into reset when the domain is powered down.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
index 527d45d12a5435724645b8871fbc13f3c5770d34..ccb30c6cdc7e2cfd14d7c0fa9c1a580c8ea21859 100644 (file)
--- a/drivers/soc/imx/imx8mp-blk-ctrl.c
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -19,6 +19,8 @@
 #define GPR_REG0               0x0
 #define  PCIE_CLOCK_MODULE_EN  BIT(0)
 #define  USB_CLOCK_MODULE_EN   BIT(1)
+#define  PCIE_PHY_APB_RST      BIT(4)
+#define  PCIE_PHY_INIT_RST     BIT(5)
 
 struct imx8mp_blk_ctrl_domain;
 
@@ -81,6 +83,10 @@ static void imx8mp_hsio_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
        case IMX8MP_HSIOBLK_PD_PCIE:
                regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
                break;
+       case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+               regmap_set_bits(bc->regmap, GPR_REG0,
+                               PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+               break;
        default:
                break;
        }
@@ -96,6 +102,10 @@ static void imx8mp_hsio_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
        case IMX8MP_HSIOBLK_PD_PCIE:
                regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
                break;
+       case IMX8MP_HSIOBLK_PD_PCIE_PHY:
+               regmap_clear_bits(bc->regmap, GPR_REG0,
+                                 PCIE_PHY_APB_RST | PCIE_PHY_INIT_RST);
+               break;
        default:
                break;
        }