}
 
        /* All playback and D0i3 compatible streams are DMI L1 capable */
-       if (direction == SNDRV_PCM_STREAM_PLAYBACK ||
+       if (IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_ALWAYS_ENABLE_DMI_L1) ||
+           direction == SNDRV_PCM_STREAM_PLAYBACK ||
            spcm->stream[substream->stream].d0i3_compatible)
                flags |= SOF_HDA_STREAM_DMI_L1_COMPATIBLE;
 
 
         * Workaround to address a known issue with host DMA that results
         * in xruns during pause/release in capture scenarios.
         */
-       if (!IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_ALWAYS_ENABLE_DMI_L1))
-               if (!(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE))
-                       snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
-                                               HDA_VS_INTEL_EM2,
-                                               HDA_VS_INTEL_EM2_L1SEN, 0);
+       if (!(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE))
+               snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
+                                       HDA_VS_INTEL_EM2,
+                                       HDA_VS_INTEL_EM2_L1SEN, 0);
 
        return stream;
 }
        spin_unlock_irq(&bus->reg_lock);
 
        /* Enable DMI L1 if permitted */
-       if (!IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_ALWAYS_ENABLE_DMI_L1) && dmi_l1_enable)
+       if (dmi_l1_enable)
                snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
                                        HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN);