uint32_t                        rev_id;
        uint32_t                        external_rev_id;
        unsigned long                   flags;
+       unsigned long                   apu_flags;
        int                             usec_timeout;
        const struct amdgpu_asic_funcs  *asic_funcs;
        bool                            shutdown;
 
                chip_name = "vega12";
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
 
                        break;
                case CHIP_RAVEN:
                        /* enable S/G on PCO and RV2 */
-                       if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
+                       if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
+                           (adev->apu_flags & AMD_APU_IS_PICASSO))
                                domain |= AMDGPU_GEM_DOMAIN_GTT;
                        break;
                default:
 
        }
 
        if (adev->asic_type == CHIP_RAVEN) {
-               if (adev->rev_id < 8) {
+               if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
                        if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
                                amdgpu_gfx_off_ctrl(adev, false);
                        else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 
 
        switch (adev->asic_type) {
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        fw_name = FIRMWARE_RAVEN2;
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        fw_name = FIRMWARE_PICASSO;
                else
                        fw_name = FIRMWARE_RAVEN;
 
        case CHIP_RAVEN:
                soc15_program_register_sequence(adev, golden_settings_gc_9_1,
                                                ARRAY_SIZE(golden_settings_gc_9_1));
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        soc15_program_register_sequence(adev,
                                                        golden_settings_gc_9_1_rv2,
                                                        ARRAY_SIZE(golden_settings_gc_9_1_rv2));
        case CHIP_VEGA20:
                break;
        case CHIP_RAVEN:
-               if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) &&
+               if (!((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
+                     (adev->apu_flags & AMD_APU_IS_PICASSO)) &&
                    ((!is_raven_kicker(adev) &&
                      adev->gfx.rlc_fw_version < 531) ||
                     (adev->gfx.rlc_feature_version < 1) ||
                chip_name = "vega20";
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
                else
                        gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
         */
        if (adev->gfx.rlc.is_rlc_v2_1) {
                if (adev->asic_type == CHIP_VEGA12 ||
-                   (adev->asic_type == CHIP_RAVEN &&
-                    adev->rev_id >= 8))
+                   (adev->apu_flags & AMD_APU_IS_RAVEN2))
                        gfx_v9_1_init_rlc_save_restore_list(adev);
                gfx_v9_0_enable_save_restore_machine(adev);
        }
                adev->gds.gds_compute_max_wave_id = 0x27f;
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 0x8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */
                else
                        adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */
 
                WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
                        min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-               if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        /*
                        * Raven2 has a HW issue that it is unable to use the
                        * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
 
        return ((vmhub == AMDGPU_MMHUB_0 ||
                 vmhub == AMDGPU_MMHUB_1) &&
                (!amdgpu_sriov_vf(adev)) &&
-               (!(adev->asic_type == CHIP_RAVEN &&
-                  adev->rev_id < 0x8 &&
-                  adev->pdev->device == 0x15d8)));
+               (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
+                  (adev->apu_flags & AMD_APU_IS_PICASSO))));
 }
 
 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 
        WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
                     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 
-       if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
+       if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                /*
                 * Raven2 has a HW issue that it is unable to use the vram which
                 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
 
 
        switch (adev->asic_type) {
        case CHIP_RAVEN:
-               if (adev->rev_id >= 0x8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
 
                soc15_program_register_sequence(adev,
                                                golden_settings_sdma_4_1,
                                                ARRAY_SIZE(golden_settings_sdma_4_1));
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        soc15_program_register_sequence(adev,
                                                        golden_settings_sdma_rv2,
                                                        ARRAY_SIZE(golden_settings_sdma_rv2));
                chip_name = "vega20";
                break;
        case CHIP_RAVEN:
-               if (adev->rev_id >= 8)
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        chip_name = "raven2";
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        chip_name = "picasso";
                else
                        chip_name = "raven";
 
 static int soc15_asic_reset(struct amdgpu_device *adev)
 {
        /* original raven doesn't have full asic reset */
-       if (adev->pdev->device == 0x15dd && adev->rev_id < 0x8)
+       if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
+           !(adev->apu_flags & AMD_APU_IS_RAVEN2))
                return 0;
 
        switch (soc15_asic_reset_method(adev)) {
                break;
        case CHIP_RAVEN:
                adev->asic_funcs = &soc15_asic_funcs;
+               if (adev->pdev->device == 0x15dd)
+                       adev->apu_flags |= AMD_APU_IS_RAVEN;
+               if (adev->pdev->device == 0x15d8)
+                       adev->apu_flags |= AMD_APU_IS_PICASSO;
                if (adev->rev_id >= 0x8)
+                       adev->apu_flags |= AMD_APU_IS_RAVEN2;
+
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2)
                        adev->external_rev_id = adev->rev_id + 0x79;
-               else if (adev->pdev->device == 0x15d8)
+               else if (adev->apu_flags & AMD_APU_IS_PICASSO)
                        adev->external_rev_id = adev->rev_id + 0x41;
                else if (adev->rev_id == 1)
                        adev->external_rev_id = adev->rev_id + 0x20;
                else
                        adev->external_rev_id = adev->rev_id + 0x01;
 
-               if (adev->rev_id >= 0x8) {
+               if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
                        adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                                AMD_CG_SUPPORT_GFX_MGLS |
                                AMD_CG_SUPPORT_GFX_CP_LS |
                                AMD_CG_SUPPORT_VCN_MGCG;
 
                        adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
-               } else if (adev->pdev->device == 0x15d8) {
+               } else if (adev->apu_flags & AMD_APU_IS_PICASSO) {
                        adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                                AMD_CG_SUPPORT_GFX_MGLS |
                                AMD_CG_SUPPORT_GFX_CP_LS |
                break;
        case CHIP_RENOIR:
                adev->asic_funcs = &soc15_asic_funcs;
+               adev->apu_flags |= AMD_APU_IS_RENOIR;
                adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
                                 AMD_CG_SUPPORT_GFX_MGLS |
                                 AMD_CG_SUPPORT_GFX_3D_CGCG |
 
        AMD_EXP_HW_SUPPORT = 0x00080000UL,
 };
 
+enum amd_apu_flags {
+       AMD_APU_IS_RAVEN = 0x00000001UL,
+       AMD_APU_IS_RAVEN2 = 0x00000002UL,
+       AMD_APU_IS_PICASSO = 0x00000004UL,
+       AMD_APU_IS_RENOIR = 0x00000008UL,
+};
+
 enum amd_ip_block_type {
        AMD_IP_BLOCK_TYPE_COMMON,
        AMD_IP_BLOCK_TYPE_GMC,
 
 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
 {
        struct amdgpu_device *adev = hwmgr->adev;
-       if ((adev->asic_type == CHIP_RAVEN) &&
-           (adev->rev_id != 0x15d8) &&
+       if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
            (hwmgr->smu_version >= 0x41e2b))
                return true;
        else
 
        smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion, &hwmgr->smu_version);
        adev->pm.fw_version = hwmgr->smu_version >> 8;
 
-       if (adev->rev_id < 0x8 && adev->pdev->device != 0x15d8 &&
+       if (!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
+           (adev->apu_flags & AMD_APU_IS_RAVEN) &&
            adev->pm.fw_version < 0x1e45)
                adev->pm.pp_feature &= ~PP_GFXOFF_MASK;