return result;
 }
 
-#define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
+#define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 
 /* controller setup */
 
        }
 
        dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
-              tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
+               tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate),
+                                               twrph1, to_ns(twrph1, clkrate));
 
        switch (info->cpu_type) {
        case TYPE_S3C2410:
        if (ret < 0)
                return ret;
 
-       switch (info->cpu_type) {
-       case TYPE_S3C2410:
+       switch (info->cpu_type) {
+       case TYPE_S3C2410:
        default:
                break;
 
-       case TYPE_S3C2440:
-       case TYPE_S3C2412:
+       case TYPE_S3C2440:
+       case TYPE_S3C2412:
                /* enable the controller and de-assert nFCE */
 
                writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
                        dev_info(info->device, "System booted from NAND\n");
 
                break;
-       }
+       }
 
        chip->IO_ADDR_R = chip->IO_ADDR_W;
 
 static int s3c24xx_nand_probe(struct platform_device *pdev)
 {
        struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
-       enum s3c_cpu_type cpu_type; 
+       enum s3c_cpu_type cpu_type;
        struct s3c2410_nand_info *info;
        struct s3c2410_nand_mtd *nmtd;
        struct s3c2410_nand_set *sets;