ci_update_uvd_dpm(rdev, gate);
 }
 
+bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
+{
+       struct ci_power_info *pi = ci_get_pi(rdev);
+       u32 vblank_time = r600_dpm_get_vblank_time(rdev);
+       u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
+
+       if (vblank_time < switch_limit)
+               return true;
+       else
+               return false;
+
+}
+
 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
                                        struct radeon_ps *rps)
 {
        u32 sclk, mclk;
        int i;
 
-       if (rdev->pm.dpm.new_active_crtc_count > 1)
+       if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
+           ci_dpm_vblank_too_short(rdev))
                disable_mclk_switching = true;
        else
                disable_mclk_switching = false;
 
                .print_power_state = &ci_dpm_print_power_state,
                .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
                .force_performance_level = &ci_dpm_force_performance_level,
+               .vblank_too_short = &ci_dpm_vblank_too_short,
        },
        .pflip = {
                .pre_page_flip = &evergreen_pre_page_flip,
 
                                                    struct seq_file *m);
 int ci_dpm_force_performance_level(struct radeon_device *rdev,
                                   enum radeon_dpm_forced_level level);
+bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
 
 int kv_dpm_init(struct radeon_device *rdev);
 int kv_dpm_enable(struct radeon_device *rdev);