ASoC: wm8904: enable MCLK in STANDBY

MCLK input is needed when accessing any register after enabling SYSCLK.

This also fixes imbalance of clk_enable / clk_disable when transitioning
between ON -> STANDBY -> ON bias levels.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c
index 9283a2dc70aa2c3220b8e78eec567370ebf607ac..9e0f96e0f8ece35a76d7cb830d8b7d4cba0894b5 100644 (file)
--- a/sound/soc/codecs/wm8904.c
+++ b/sound/soc/codecs/wm8904.c
@@ -1837,9 +1837,6 @@ static int wm8904_set_bias_level(struct snd_soc_component *component,
 
        switch (level) {
        case SND_SOC_BIAS_ON:
-               ret = clk_prepare_enable(wm8904->mclk);
-               if (ret)
-                       return ret;
                break;
 
        case SND_SOC_BIAS_PREPARE:
@@ -1864,6 +1861,15 @@ static int wm8904_set_bias_level(struct snd_soc_component *component,
                                return ret;
                        }
 
+                       ret = clk_prepare_enable(wm8904->mclk);
+                       if (ret) {
+                               dev_err(component->dev,
+                                       "Failed to enable MCLK: %d\n", ret);
+                               regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
+                                                      wm8904->supplies);
+                               return ret;
+                       }
+
                        regcache_cache_only(wm8904->regmap, false);
                        regcache_sync(wm8904->regmap);