mmc: omap: clarify DDR timing mode between SD-UHS and eMMC

Replaced UHS_DDR50 with MMC_DDR52.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>

diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index e91ee21549d03ad22c2bcf2287f61074cc3d889b..b4de63bf10fdfde09e374f90e06923616352e0c2 100644 (file)
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -582,7 +582,7 @@ static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
         *      - MMC/SD clock coming out of controller > 25MHz
         */
        if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
-           (ios->timing != MMC_TIMING_UHS_DDR50) &&
+           (ios->timing != MMC_TIMING_MMC_DDR52) &&
            ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
                regval = OMAP_HSMMC_READ(host->base, HCTL);
                if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
@@ -602,7 +602,7 @@ static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
        u32 con;
 
        con = OMAP_HSMMC_READ(host->base, CON);
-       if (ios->timing == MMC_TIMING_UHS_DDR50)
+       if (ios->timing == MMC_TIMING_MMC_DDR52)
                con |= DDR;     /* configure in DDR mode */
        else
                con &= ~DDR;