/* Called when pci_enable_device() is called. Returns true to
         * allow assignment/enabling of the device. */
        bool            (*enable_device_hook)(struct pci_dev *);
+
+       /* Called during PCI resource reassignment */
+       resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
 };
 
 /*
        return true;
 }
 
+static inline resource_size_t pci_window_alignment(struct pci_bus *bus,
+                                                  unsigned long type)
+{
+       struct pci_controller *phb = pci_bus_to_host(bus);
+
+       if (phb->controller_ops.window_alignment)
+               return phb->controller_ops.window_alignment(bus, type);
+       if (ppc_md.pcibios_window_alignment)
+               return ppc_md.pcibios_window_alignment(bus, type);
+
+       /*
+        * PCI core will figure out the default
+        * alignment: 4KiB for I/O and 1MiB for
+        * memory window.
+        */
+       return 1;
+}
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_PCI_BRIDGE_H */
 
 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
                                         unsigned long type)
 {
-       if (ppc_md.pcibios_window_alignment)
-               return ppc_md.pcibios_window_alignment(bus, type);
-
-       /*
-        * PCI core will figure out the default
-        * alignment: 4KiB for I/O and 1MiB for
-        * memory window.
-        */
-       return 1;
+       return pci_window_alignment(bus, type);
 }
 
 void pcibios_reset_secondary_bus(struct pci_dev *dev)