}
 
 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
-                                   int link, int speed, int duplex,
+                                   int link, int speed, int duplex, int pause,
                                    phy_interface_t mode)
 {
        int err;
                        goto restore_link;
        }
 
+       if (chip->info->ops->port_set_pause) {
+               err = chip->info->ops->port_set_pause(chip, port, pause);
+               if (err)
+                       goto restore_link;
+       }
+
        if (chip->info->ops->port_set_duplex) {
                err = chip->info->ops->port_set_duplex(chip, port, duplex);
                if (err && err != -EOPNOTSUPP)
 
        mutex_lock(&chip->reg_lock);
        err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
-                                      phydev->duplex, phydev->interface);
+                                      phydev->duplex, phydev->pause,
+                                      phydev->interface);
        mutex_unlock(&chip->reg_lock);
 
        if (err && err != -EOPNOTSUPP)
                                 const struct phylink_link_state *state)
 {
        struct mv88e6xxx_chip *chip = ds->priv;
-       int speed, duplex, link, err;
+       int speed, duplex, link, pause, err;
 
        if (mode == MLO_AN_PHY)
                return;
                duplex = DUPLEX_UNFORCED;
                link = LINK_UNFORCED;
        }
+       pause = !!phylink_test(state->advertising, Pause);
 
        mutex_lock(&chip->reg_lock);
-       err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex,
+       err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
                                       state->interface);
        mutex_unlock(&chip->reg_lock);
 
        if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
                err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
                                               SPEED_MAX, DUPLEX_FULL,
+                                              PAUSE_OFF,
                                               PHY_INTERFACE_MODE_NA);
        else
                err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
                                               SPEED_UNFORCED, DUPLEX_UNFORCED,
+                                              PAUSE_ON,
                                               PHY_INTERFACE_MODE_NA);
        if (err)
                return err;
        .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
        .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
        .port_pause_limit = mv88e6097_port_pause_limit,
+       .port_set_pause = mv88e6185_port_set_pause,
        .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
        .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
        .stats_get_sset_count = mv88e6095_stats_get_sset_count,
        .port_set_egress_floods = mv88e6185_port_set_egress_floods,
        .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
        .port_set_upstream_port = mv88e6095_port_set_upstream_port,
+       .port_set_pause = mv88e6185_port_set_pause,
        .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
        .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
        .stats_get_sset_count = mv88e6095_stats_get_sset_count,
 
        return mv88e6xxx_write(chip, addr, reg, val);
 }
 
+/* Offset 0x00: MAC (or PCS or Physical) Status Register
+ *
+ * For most devices, this is read only. However the 6185 has the MyPause
+ * bit read/write.
+ */
+int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
+                            int pause)
+{
+       u16 reg;
+       int err;
+
+       err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
+       if (err)
+               return err;
+
+       if (pause)
+               reg |= MV88E6XXX_PORT_STS_MY_PAUSE;
+       else
+               reg &= ~MV88E6XXX_PORT_STS_MY_PAUSE;
+
+       return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_STS, reg);
+}
+
 /* Offset 0x01: MAC (or PCS or Physical) Control Register
  *
  * Link, Duplex and Flow Control have one force bit, one value bit.