drm/panfrost: Set regulators on/off during system sleep on MediaTek SoCs

All of the MediaTek SoCs supported by Panfrost can completely cut power
to the GPU during full system sleep without any user-noticeable delay
in the resume operation, as shown by measurements taken on multiple
MediaTek SoCs (MT8183/86/92/95).

As an example, for MT8195 - a "before" with only runtime PM operations
(so, without turning on/off regulators), and an "after" executing both
the system sleep .resume() handler and .runtime_resume() (so the time
refers to T_Resume + T_Runtime_Resume):

Average Panfrost-only system sleep resume time, before: ~33500ns
Average Panfrost-only system sleep resume time, after:  ~336200ns

Keep in mind that this additional ~308200 nanoseconds delay happens only
in resume from a full system suspend, and not in runtime PM operations,
hence it is acceptable.

Measurements were also taken on MT8186, showing a delay of ~312000 ns.

Testing of this happened on all of the aforementioned MediaTek SoCs, but:
MT8183 got tested only by KernelCI with <=10 suspend/resume cycles
MT8186, MT8192, MT8195 were tested manually with over 100 suspend/resume
cycles with GNOME DE (Mutter + Wayland).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
Signed-off-by: Steven Price <steven.price@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231109102543.42971-7-angelogioacchino.delregno@collabora.com

diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 6d2897c03a8f64d45a14a24605293d8fd235d148..7a628e89d379a5fc3f71b131284b1afe9ccbbcb8 100644 (file)
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -730,7 +730,7 @@ static const struct panfrost_compatible mediatek_mt8183_b_data = {
        .supply_names = mediatek_mt8183_b_supplies,
        .num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains),
        .pm_domain_names = mediatek_mt8183_pm_domains,
-       .pm_features = BIT(GPU_PM_CLK_DIS),
+       .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 };
 
 static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" };
@@ -739,7 +739,7 @@ static const struct panfrost_compatible mediatek_mt8186_data = {
        .supply_names = mediatek_mt8183_b_supplies,
        .num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains),
        .pm_domain_names = mediatek_mt8186_pm_domains,
-       .pm_features = BIT(GPU_PM_CLK_DIS),
+       .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 };
 
 static const char * const mediatek_mt8192_supplies[] = { "mali", NULL };
@@ -750,7 +750,7 @@ static const struct panfrost_compatible mediatek_mt8192_data = {
        .supply_names = mediatek_mt8192_supplies,
        .num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains),
        .pm_domain_names = mediatek_mt8192_pm_domains,
-       .pm_features = BIT(GPU_PM_CLK_DIS),
+       .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 };
 
 static const struct of_device_id dt_match[] = {