/* 6.o Configure and enable FEC if needed */
        intel_ddi_enable_fec(encoder, crtc_state);
 
-       intel_dsc_dp_pps_write(encoder, crtc_state);
+       if (!is_mst)
+               intel_dsc_dp_pps_write(encoder, crtc_state);
 }
 
 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
        /* 7.l Configure and enable FEC if needed */
        intel_ddi_enable_fec(encoder, crtc_state);
 
-       intel_dsc_dp_pps_write(encoder, crtc_state);
+       if (!is_mst)
+               intel_dsc_dp_pps_write(encoder, crtc_state);
 }
 
 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
 
        intel_ddi_enable_fec(encoder, crtc_state);
 
-       if (!is_mst)
+       if (!is_mst) {
                intel_ddi_enable_transcoder_clock(encoder, crtc_state);
-
-       intel_dsc_dp_pps_write(encoder, crtc_state);
+               intel_dsc_dp_pps_write(encoder, crtc_state);
+       }
 }
 
 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
 
        if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
                intel_ddi_enable_transcoder_clock(encoder, pipe_config);
 
+       intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
        intel_ddi_set_dp_msa(pipe_config, conn_state);
 }