]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
drm/amdgpu : Add hive ras recovery check
authorAsad Kamal <asad.kamal@amd.com>
Thu, 5 Oct 2023 07:40:42 +0000 (15:40 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 19 Oct 2023 22:26:51 +0000 (18:26 -0400)
If one of the devices in the hive detects a
fatal error, need to send ras recovery reset
message to PMFW of all devices in the hive.
For that add a flag in hive to indicate that
it's undergoing ras recovery

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

index 973073e07b2a6ddbc2974aab385f2d4a4a8866b0..c7f8dcb3b4d2d3d7d84fd4274748e74f0598a72c 100644 (file)
@@ -2140,9 +2140,11 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
        struct amdgpu_device *remote_adev = NULL;
        struct amdgpu_device *adev = ras->adev;
        struct list_head device_list, *device_list_handle =  NULL;
+       struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
 
+       if (hive)
+               atomic_set(&hive->ras_recovery, 1);
        if (!ras->disable_ras_err_cnt_harvest) {
-               struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
 
                /* Build list of devices to query RAS related errors */
                if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
@@ -2159,7 +2161,6 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
                        amdgpu_ras_log_on_err_counter(remote_adev);
                }
 
-               amdgpu_put_xgmi_hive(hive);
        }
 
        if (amdgpu_device_should_recover_gpu(ras->adev)) {
@@ -2194,6 +2195,10 @@ static void amdgpu_ras_do_recovery(struct work_struct *work)
                amdgpu_device_gpu_recover(ras->adev, NULL, &reset_context);
        }
        atomic_set(&ras->in_recovery, 0);
+       if (hive) {
+               atomic_set(&hive->ras_recovery, 0);
+               amdgpu_put_xgmi_hive(hive);
+       }
 }
 
 /* alloc/realloc bps array */
index 86fbf56938f4cdb7e8216c24ed3cda5e8013f28a..6cab882e8061e80f33bca5eb1a7b59d8cf0a687f 100644 (file)
@@ -44,6 +44,7 @@ struct amdgpu_hive_info {
 
        struct amdgpu_reset_domain *reset_domain;
        uint32_t device_remove_count;
+       atomic_t ras_recovery;
 };
 
 struct amdgpu_pcs_ras_field {
index 74fc945a8f9b71c4acbe0572e51d765d8fa70b59..c2efb0d24bf8a1ea42e1eefbe5662d966b428f14 100644 (file)
@@ -2238,16 +2238,24 @@ failed:
 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
+       struct amdgpu_hive_info *hive = NULL;
+       u32 hive_ras_recovery = 0;
        struct amdgpu_ras *ras;
        u32 fatal_err, param;
        int ret = 0;
 
+       hive = amdgpu_get_xgmi_hive(adev);
        ras = amdgpu_ras_get_context(adev);
        fatal_err = 0;
        param = SMU_RESET_MODE_1;
 
+       if (hive) {
+               hive_ras_recovery = atomic_read(&hive->ras_recovery);
+               amdgpu_put_xgmi_hive(hive);
+       }
+
        /* fatal error triggered by ras, PMFW supports the flag */
-       if (ras && atomic_read(&ras->in_recovery))
+       if (ras && (atomic_read(&ras->in_recovery) || hive_ras_recovery))
                fatal_err = 1;
 
        param |= (fatal_err << 16);