hwmgr->dyn_state.vddc_dependency_on_sclk;
        unsigned long clock = 0, level;
 
-       if (NULL == table && table->count <= 0)
+       if (NULL == table || table->count <= 0)
                return -EINVAL;
 
        cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
                                hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
        unsigned long clock = 0, level;
 
-       if (NULL == table && table->count <= 0)
+       if (NULL == table || table->count <= 0)
                return -EINVAL;
 
        cz_hwmgr->uvd_dpm.soft_min_clk = 0;
                                hwmgr->dyn_state.vce_clock_voltage_dependency_table;
        unsigned long clock = 0, level;
 
-       if (NULL == table && table->count <= 0)
+       if (NULL == table || table->count <= 0)
                return -EINVAL;
 
        cz_hwmgr->vce_dpm.soft_min_clk = 0;
                                hwmgr->dyn_state.acp_clock_voltage_dependency_table;
        unsigned long clock = 0, level;
 
-       if (NULL == table && table->count <= 0)
+       if (NULL == table || table->count <= 0)
                return -EINVAL;
 
        cz_hwmgr->acp_dpm.soft_min_clk = 0;
                                hwmgr->dyn_state.vddc_dependency_on_sclk;
        unsigned long clock = 0, level;
 
-       if (NULL == table && table->count <= 0)
+       if (NULL == table || table->count <= 0)
                return -EINVAL;
 
        cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;