arm64: dts: qcom: sm6350: Add TLMM block node

Add TLMM pinctrl node to enable referencing the SoC pins in other nodes.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210923162204.21752-6-konrad.dybcio@somainline.org

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 9934ecec1bb21365c2383eca316c5a9771efff5e..68de0beb9b01a4eff094538f7ad4214e26701df1 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -404,6 +404,25 @@
                        interrupt-controller;
                };
 
+               tlmm: pinctrl@f100000 {
+                       compatible = "qcom,sm6350-tlmm";
+                       reg = <0 0x0f100000 0 0x300000>;
+                       interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       gpio-ranges = <&tlmm 0 0 157>;
+               };
+
                intc: interrupt-controller@17a00000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <3>;