arm64: dts: rockchip: Enable eDP0 display on RK3588S EVB1 board

Add the necessary DT changes to enable eDP0 on RK3588S EVB1 board:
- Set pinctrl of pwm12 for backlight
- Enable edp0/hdptxphy0/vp2
- Assign the parent of DCLK_VOP2_SRC to PLL_V0PLL
- Add aux-bus/panel nodes

For RK3588, the PLL_V0PLL is specifically designed for the VOP2. This
means the clock rate of PLL_V0PLL can be adjusted according to the dclk
rate of relevant VP. It is typically assigned as the dclk source of a
specific VP when the clock of relevant display mode is unusual, such as
the eDP panel 'lg,lp079qx1-sp0v' paired with RK3588S EVB1, which has a
clock rate of 202.02MHz.

Additionally, the 'force-hpd' is set for edp0 because the HPD pin on the
panel side is not connected to the eDP HPD pin on the SoC side according
to the RK3588S EVB1 hardware design.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Link: https://lore.kernel.org/r/20250310104114.2608063-14-damon.ding@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
index 9f4aca9c2e3f9780802912da9211a9e872f7eb20..0df3e80f2dd91412c130198e49170eb19b2f5c2e 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-evb1-v10.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include <dt-bindings/usb/pd.h>
 #include "rk3588s.dtsi"
 
@@ -238,6 +239,42 @@
        status = "okay";
 };
 
+&edp0 {
+       force-hpd;
+       status = "okay";
+
+       aux-bus {
+               panel {
+                       compatible = "edp-panel";
+                       backlight = <&backlight>;
+                       power-supply = <&vcc3v3_lcd_edp>;
+                       no-hpd;
+
+                       port {
+                               panel_in_edp: endpoint {
+                                       remote-endpoint = <&edp_out_panel>;
+                               };
+                       };
+               };
+       };
+};
+
+&edp0_in {
+       edp0_in_vp2: endpoint {
+               remote-endpoint = <&vp2_out_edp0>;
+       };
+};
+
+&edp0_out {
+       edp_out_panel: endpoint {
+               remote-endpoint = <&panel_in_edp>;
+       };
+};
+
+&hdptxphy0 {
+       status = "okay";
+};
+
 &i2c3 {
        status = "okay";
 
@@ -403,6 +440,7 @@
 };
 
 &pwm12 {
+       pinctrl-0 = <&pwm12m1_pins>;
        status = "okay";
 };
 
@@ -1172,3 +1210,20 @@
                };
        };
 };
+
+&vop_mmu {
+       status = "okay";
+};
+
+&vop {
+       assigned-clocks = <&cru DCLK_VOP2_SRC>;
+       assigned-clock-parents = <&cru PLL_V0PLL>;
+       status = "okay";
+};
+
+&vp2 {
+       vp2_out_edp0: endpoint@ROCKCHIP_VOP2_EP_EDP0 {
+               reg = <ROCKCHIP_VOP2_EP_EDP0>;
+               remote-endpoint = <&edp0_in_vp2>;
+       };
+};