pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-       clk_pll_ops.enable = clk_gate_ops.enable;
-       clk_pll_ops.disable = clk_gate_ops.disable;
 
        clk = clk_register(NULL, &pll_clk->hw.hw);
        if (WARN_ON(IS_ERR(clk))) {
 
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER;
-       clk_pll_ops.enable = clk_gate_ops.enable;
-       clk_pll_ops.disable = clk_gate_ops.disable;
 
        clk = clk_register(NULL, &pll_clk->hw.hw);
        if (WARN_ON(IS_ERR(clk))) {
 
        pll_clk->hw.hw.init = &init;
 
        pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
-       clk_pll_ops.enable = clk_gate_ops.enable;
-       clk_pll_ops.disable = clk_gate_ops.disable;
 
        clk = clk_register(NULL, &pll_clk->hw.hw);
        if (WARN_ON(IS_ERR(clk))) {