return flags;
}
+static u32 ath11k_map_fw_phy_flags(u32 phy_flags)
+{
+ u32 flags = 0;
+
+ if (phy_flags & ATH11K_REG_PHY_BITMAP_NO11AX)
+ flags |= NL80211_RRF_NO_HE;
+
+ return flags;
+}
+
static bool
ath11k_reg_can_intersect(struct ieee80211_reg_rule *rule1,
struct ieee80211_reg_rule *rule2)
}
flags |= ath11k_map_fw_reg_flags(reg_rule->flags);
+ flags |= ath11k_map_fw_phy_flags(reg_info->phybitmap);
ath11k_reg_update_rule(tmp_regd->reg_rules + i,
reg_rule->start_freq,
ATH11K_DFS_REG_UNDEF,
};
+/* Phy bitmaps */
+#define ATH11K_REG_PHY_BITMAP_NO11AX BIT(5)
+
/* ATH11K Regulatory API's */
void ath11k_reg_init(struct ath11k *ar);
void ath11k_reg_free(struct ath11k_base *ab);
}
ath11k_dbg(ab, ATH11K_DBG_WMI,
- "cc_ext %s dsf %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d",
+ "cc_ext %s dfs %d BW: min_2ghz %d max_2ghz %d min_5ghz %d max_5ghz %d phy_bitmap 0x%x",
reg_info->alpha2, reg_info->dfs_region,
reg_info->min_bw_2ghz, reg_info->max_bw_2ghz,
- reg_info->min_bw_5ghz, reg_info->max_bw_5ghz);
+ reg_info->min_bw_5ghz, reg_info->max_bw_5ghz,
+ reg_info->phybitmap);
ath11k_dbg(ab, ATH11K_DBG_WMI,
"num_2ghz_reg_rules %d num_5ghz_reg_rules %d",