/* Due to lack of space, no more new filters can be programmed */
        if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
                return;
+       if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) {
+               /* HW ATR eviction will take care of removing filters on FIN
+                * and RST packets.
+                */
+               if (th->fin || th->rst)
+                       return;
+       }
 
        tx_ring->atr_count++;
 
                        I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
                        I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
 
+       if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
+               dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
+
        fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
        fdir_desc->rsvd = cpu_to_le32(0);
        fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
 
 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
                                          I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
 
+#define I40E_TXD_FLTR_QW1_ATR_SHIFT    (0xEULL + \
+                                        I40E_TXD_FLTR_QW1_CMD_SHIFT)
+#define I40E_TXD_FLTR_QW1_ATR_MASK     BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
+
 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK        (0x1FFUL << \
                                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)