clk: sunxi-ng: a64: Add constraints on PLL-MIPI's n/m ratio and parent rate

The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
 - M/N <= 3
 - (PLL_VIDEO0)/M >= 24MHz

Use these constraints.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
Link: https://lore.kernel.org/r/20240310-pinephone-pll-fixes-v4-4-46fc80c83637@oltmanns.dev
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 8951ffc14ff52c5a2bd7d6be60f47539cad36fb1..df679dada792a81efca829b0a0e9a31141b98b28 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -171,11 +171,13 @@ static struct ccu_nkm pll_mipi_clk = {
         * user manual, and by experiments the PLL doesn't work without
         * these bits toggled.
         */
-       .enable         = BIT(31) | BIT(23) | BIT(22),
-       .lock           = BIT(28),
-       .n              = _SUNXI_CCU_MULT(8, 4),
-       .k              = _SUNXI_CCU_MULT_MIN(4, 2, 2),
-       .m              = _SUNXI_CCU_DIV(0, 4),
+       .enable                 = BIT(31) | BIT(23) | BIT(22),
+       .lock                   = BIT(28),
+       .n                      = _SUNXI_CCU_MULT(8, 4),
+       .k                      = _SUNXI_CCU_MULT_MIN(4, 2, 2),
+       .m                      = _SUNXI_CCU_DIV(0, 4),
+       .max_m_n_ratio          = 3,
+       .min_parent_m_ratio     = 24000000,
        .common         = {
                .reg            = 0x040,
                .hw.init        = CLK_HW_INIT("pll-mipi", "pll-video0",