tx_ring->dcb_tc = 0;
                if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
                        tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
+               if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
+                       tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
                vsi->tx_rings[i] = tx_ring;
 
                rx_ring = &tx_ring[1];
 
         * so the total length of IPv4 header is IHL*4 bytes
         * The UDP_0 bit *may* bet set if the *inner* header is UDP
         */
-       if (ipv4_tunnel) {
+       if (!(vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE) &&
+           (ipv4_tunnel)) {
                skb->transport_header = skb->mac_header +
                                        sizeof(struct ethhdr) +
                                        (ip_hdr(skb)->ihl * 4);
        struct iphdr *this_ip_hdr;
        u32 network_hdr_len;
        u8 l4_hdr = 0;
+       struct udphdr *oudph;
+       struct iphdr *oiph;
        u32 l4_tunnel = 0;
 
        if (skb->encapsulation) {
                switch (ip_hdr(skb)->protocol) {
                case IPPROTO_UDP:
+                       oudph = udp_hdr(skb);
+                       oiph = ip_hdr(skb);
                        l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
                        *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
                        break;
                        *tx_flags &= ~I40E_TX_FLAGS_IPV4;
                        *tx_flags |= I40E_TX_FLAGS_IPV6;
                }
+               if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
+                   (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
+                   (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
+                       oudph->check = ~csum_tcpudp_magic(oiph->saddr,
+                                       oiph->daddr,
+                                       (skb->len - skb_transport_offset(skb)),
+                                       IPPROTO_UDP, 0);
+                       *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
+               }
        } else {
                network_hdr_len = skb_network_header_len(skb);
                this_ip_hdr = ip_hdr(skb);
 
 
        u16 flags;
 #define I40E_TXR_FLAGS_WB_ON_ITR       BIT(0)
+#define I40E_TXR_FLAGS_OUTER_UDP_CSUM  BIT(1)
+
        /* stats structs */
        struct i40e_queue_stats stats;
        struct u64_stats_sync syncp;
 
        I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
        I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
        I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
-       I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
+       /* Note: Bit 8 is reserved in X710 and XL710 */
+       I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
        I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
        I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
        I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
        I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
        I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
        I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
-       I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
+       /* Note: For non-tunnel packets INT_UDP_0 is the right status for
+        * UDP header
+        */
+       I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
        I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 };
 
 #define I40E_TXD_CTX_QW0_DECTTL_MASK   (0xFULL << \
                                         I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 
+#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT  23
+#define I40E_TXD_CTX_QW0_L4T_CS_MASK   BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
 struct i40e_filter_program_desc {
        __le32 qindex_flex_ptype_vsi;
        __le32 rsvd;
 
        struct iphdr *this_ip_hdr;
        u32 network_hdr_len;
        u8 l4_hdr = 0;
+       struct udphdr *oudph;
+       struct iphdr *oiph;
        u32 l4_tunnel = 0;
 
        if (skb->encapsulation) {
                switch (ip_hdr(skb)->protocol) {
                case IPPROTO_UDP:
+                       oudph = udp_hdr(skb);
+                       oiph = ip_hdr(skb);
                        l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
                        *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
                        break;
                }
 
 
+               if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
+                   (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING)        &&
+                   (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
+                       oudph->check = ~csum_tcpudp_magic(oiph->saddr,
+                                       oiph->daddr,
+                                       (skb->len - skb_transport_offset(skb)),
+                                       IPPROTO_UDP, 0);
+                       *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
+               }
        } else {
                network_hdr_len = skb_network_header_len(skb);
                this_ip_hdr = ip_hdr(skb);
 
 
        u16 flags;
 #define I40E_TXR_FLAGS_WB_ON_ITR       BIT(0)
+#define I40E_TXR_FLAGS_OUTER_UDP_CSUM  BIT(1)
+
        /* stats structs */
        struct i40e_queue_stats stats;
        struct u64_stats_sync syncp;
 
        I40E_RX_DESC_STATUS_CRCP_SHIFT          = 4,
        I40E_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
        I40E_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
-       I40E_RX_DESC_STATUS_PIF_SHIFT           = 8,
+       /* Note: Bit 8 is reserved in X710 and XL710 */
+       I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
        I40E_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
        I40E_RX_DESC_STATUS_FLM_SHIFT           = 11,
        I40E_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
        I40E_RX_DESC_STATUS_LPBK_SHIFT          = 14,
        I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
        I40E_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
-       I40E_RX_DESC_STATUS_UDP_0_SHIFT         = 18,
+       /* Note: For non-tunnel packets INT_UDP_0 is the right status for
+        * UDP header
+        */
+       I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
        I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 };
 
 #define I40E_TXD_CTX_QW0_DECTTL_MASK   (0xFULL << \
                                         I40E_TXD_CTX_QW0_DECTTL_SHIFT)
 
+#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT  23
+#define I40E_TXD_CTX_QW0_L4T_CS_MASK   BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
 struct i40e_filter_program_desc {
        __le32 qindex_flex_ptype_vsi;
        __le32 rsvd;