pclk = of_clk_get_by_name(np, "pclk");
        if (IS_ERR(pclk)) {
                pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
-               return;
+               goto out_unmap;
        }
 
        if (clk_prepare_enable(pclk)) {
                pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
-               return;
+               goto out_unmap;
        }
 
        timer_clk = of_clk_get_by_name(np, "timer");
        if (IS_ERR(timer_clk)) {
                pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
-               return;
+               goto out_timer_clk;
        }
 
        if (clk_prepare_enable(timer_clk)) {
                pr_err("Failed to enable timer clock\n");
-               return;
+               goto out_timer_clk;
        }
 
        bc_timer.freq = clk_get_rate(timer_clk);
        irq = irq_of_parse_and_map(np, 0);
        if (!irq) {
                pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
-               return;
+               goto out_irq;
        }
 
        ce->name = TIMER_NAME;
        ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
        if (ret) {
                pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
-               return;
+               goto out_irq;
        }
 
        clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
+
+       return;
+
+out_irq:
+       clk_disable_unprepare(timer_clk);
+out_timer_clk:
+       clk_disable_unprepare(pclk);
+out_unmap:
+       iounmap(bc_timer.base);
 }
 
 CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init);