drm/xe: Use write-back caching mode for system memory on DGFX

The caching mode for buffer objects with VRAM as a possible
placement was forced to write-combined, regardless of placement.

However, write-combined system memory is expensive to allocate and
even though it is pooled, the pool is expensive to shrink, since
it involves global CPU TLB flushes.

Moreover write-combined system memory from TTM is only reliably
available on x86 and DGFX doesn't have an x86 restriction.

So regardless of the cpu caching mode selected for a bo,
internally use write-back caching mode for system memory on DGFX.

Coherency is maintained, but user-space clients may perceive a
difference in cpu access speeds.

v2:
- Update RB- and Ack tags.
- Rephrase wording in xe_drm.h (Matt Roper)
v3:
- Really rephrase wording.

Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Fixes: 622f709ca629 ("drm/xe/uapi: Add support for CPU caching mode")
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Effie Yu <effie.yu@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Jose Souza <jose.souza@intel.com>
Cc: Michal Mrozek <michal.mrozek@intel.com>
Cc: <stable@vger.kernel.org> # v6.8+
Acked-by: Matthew Auld <matthew.auld@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Fixes: 622f709ca629 ("drm/xe/uapi: Add support for CPU caching mode")
Acked-by: Michal Mrozek <michal.mrozek@intel.com>
Acked-by: Effie Yu <effie.yu@intel.com> #On chat
Link: https://patchwork.freedesktop.org/patch/msgid/20240705132828.27714-1-thomas.hellstrom@linux.intel.com
(cherry picked from commit 01e0cfc994be484ddcb9e121e353e51d8bb837c0)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index bc1f794e3e614e70aca3345cfddf1a44b72152fb..b6f3a43d637f704e8cbd4e7f6e66202607037ec8 100644 (file)
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -317,7 +317,7 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
        struct xe_device *xe = xe_bo_device(bo);
        struct xe_ttm_tt *tt;
        unsigned long extra_pages;
-       enum ttm_caching caching;
+       enum ttm_caching caching = ttm_cached;
        int err;
 
        tt = kzalloc(sizeof(*tt), GFP_KERNEL);
@@ -331,26 +331,35 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
                extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo->size),
                                           PAGE_SIZE);
 
-       switch (bo->cpu_caching) {
-       case DRM_XE_GEM_CPU_CACHING_WC:
-               caching = ttm_write_combined;
-               break;
-       default:
-               caching = ttm_cached;
-               break;
-       }
-
-       WARN_ON((bo->flags & XE_BO_FLAG_USER) && !bo->cpu_caching);
-
        /*
-        * Display scanout is always non-coherent with the CPU cache.
-        *
-        * For Xe_LPG and beyond, PPGTT PTE lookups are also non-coherent and
-        * require a CPU:WC mapping.
+        * DGFX system memory is always WB / ttm_cached, since
+        * other caching modes are only supported on x86. DGFX
+        * GPU system memory accesses are always coherent with the
+        * CPU.
         */
-       if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
-           (xe->info.graphics_verx100 >= 1270 && bo->flags & XE_BO_FLAG_PAGETABLE))
-               caching = ttm_write_combined;
+       if (!IS_DGFX(xe)) {
+               switch (bo->cpu_caching) {
+               case DRM_XE_GEM_CPU_CACHING_WC:
+                       caching = ttm_write_combined;
+                       break;
+               default:
+                       caching = ttm_cached;
+                       break;
+               }
+
+               WARN_ON((bo->flags & XE_BO_FLAG_USER) && !bo->cpu_caching);
+
+               /*
+                * Display scanout is always non-coherent with the CPU cache.
+                *
+                * For Xe_LPG and beyond, PPGTT PTE lookups are also
+                * non-coherent and require a CPU:WC mapping.
+                */
+               if ((!bo->cpu_caching && bo->flags & XE_BO_FLAG_SCANOUT) ||
+                   (xe->info.graphics_verx100 >= 1270 &&
+                    bo->flags & XE_BO_FLAG_PAGETABLE))
+                       caching = ttm_write_combined;
+       }
 
        err = ttm_tt_init(&tt->ttm, &bo->ttm, page_flags, caching, extra_pages);
        if (err) {

diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index 86422e113d39625043e16780a831b718f3464584..10450f1fbbde7fa66db3f676d6f5fa0fcde78627 100644 (file)
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -66,7 +66,8 @@ struct xe_bo {
 
        /**
         * @cpu_caching: CPU caching mode. Currently only used for userspace
-        * objects.
+        * objects. Exceptions are system memory on DGFX, which is always
+        * WB.
         */
        u16 cpu_caching;
 

diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 1446c3bae5159e29ae5a637e4fb423983f352284..d425b83181df9f47c4c8719eb894d05d514d9f78 100644 (file)
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -776,7 +776,13 @@ struct drm_xe_gem_create {
 #define DRM_XE_GEM_CPU_CACHING_WC                      2
        /**
         * @cpu_caching: The CPU caching mode to select for this object. If
-        * mmaping the object the mode selected here will also be used.
+        * mmaping the object the mode selected here will also be used. The
+        * exception is when mapping system memory (including data evicted
+        * to system) on discrete GPUs. The caching mode selected will
+        * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
+        * between GPU- and CPU is guaranteed. The caching mode of
+        * existing CPU-mappings will be updated transparently to
+        * user-space clients.
         */
        __u16 cpu_caching;
        /** @pad: MBZ */