clk: mediatek: update clock driver of MT2712

According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 991d4093726e5c1a191af47895a2dd247a53f9dc..e36f4aab634da5ad63481dc4c350397cf9a50576 100644 (file)
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -223,6 +223,8 @@ static const struct mtk_fixed_factor top_divs[] = {
                4),
        FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
                3),
+       FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
+               3),
 };
 
 static const char * const axi_parents[] = {
@@ -594,7 +596,8 @@ static const char * const a1sys_hp_parents[] = {
        "apll1_ck",
        "apll1_d2",
        "apll1_d4",
-       "apll1_d8"
+       "apll1_d8",
+       "apll1_d3"
 };
 
 static const char * const a2sys_hp_parents[] = {
@@ -602,7 +605,8 @@ static const char * const a2sys_hp_parents[] = {
        "apll2_ck",
        "apll2_d2",
        "apll2_d4",
-       "apll2_d8"
+       "apll2_d8",
+       "apll2_d3"
 };
 
 static const char * const asm_l_parents[] = {