amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID

Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch ignores a .force_clk_levels(SMU_DCEFCLK) call and issues an
info message.

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index f827096dc849a0079f7ac0ab22437389eeeffc97..ac13042672ea1094e1bc1b9b64e9a68d25ff7ac6 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1443,7 +1443,6 @@ static int navi10_force_clk_levels(struct smu_context *smu,
        case SMU_SOCCLK:
        case SMU_MCLK:
        case SMU_UCLK:
-       case SMU_DCEFCLK:
        case SMU_FCLK:
                /* There is only 2 levels for fine grained DPM */
                if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1463,6 +1462,10 @@ static int navi10_force_clk_levels(struct smu_context *smu,
                if (ret)
                        return size;
                break;
+       case SMU_DCEFCLK:
+               dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+               break;
+
        default:
                break;
        }

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 72d9c1be1835c258b02ad5c41d99dbc5a521e417..d2fd44b903ca415274756d7d7bcd634c82950717 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1127,7 +1127,6 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
        case SMU_SOCCLK:
        case SMU_MCLK:
        case SMU_UCLK:
-       case SMU_DCEFCLK:
        case SMU_FCLK:
                /* There is only 2 levels for fine grained DPM */
                if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
@@ -1147,6 +1146,9 @@ static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
                if (ret)
                        goto forec_level_out;
                break;
+       case SMU_DCEFCLK:
+               dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
+               break;
        default:
                break;
        }