/*
  *  linux/arch/arm/mach-omap1/clock.c
  *
- *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
+ *  Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *
  *  Modified to use omap shared clock framework by
 
 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
 {
-       if (clk->flags & RATE_FIXED)
-               return clk->rate;
-
        if (clk->round_rate != NULL)
                return clk->round_rate(clk, rate);
 
 
 /*
  *  linux/arch/arm/mach-omap1/clock_data.c
  *
- *  Copyright (C) 2004 - 2005, 2009 Nokia corporation
+ *  Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
  *
 static struct clk dummy_ck = {
        .name   = "dummy",
        .ops    = &clkops_dummy,
-       .flags  = RATE_FIXED,
 };
 
 static struct clk ck_ref = {
                /* Direct from ULPD, no real parent */
                .parent         = &armper_ck.clk,
                .rate           = 48000000,
-               .flags          = RATE_FIXED | ENABLE_REG_32BIT |
-                                 CLOCK_NO_IDLE_PARENT,
+               .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
                .enable_bit     = 29,
        },
                /* Direct from ULPD, no real parent */
                .parent         = &armper_ck.clk,
                .rate           = 48000000,
-               .flags          = RATE_FIXED | ENABLE_REG_32BIT |
-                                 CLOCK_NO_IDLE_PARENT,
+               .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
                .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
                .enable_bit     = 31,
        },
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent */
        .rate           = 6000000,
-       .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+       .flags          = ENABLE_REG_32BIT,
        .enable_reg     = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
        .enable_bit     = USB_MCLK_EN_BIT,
 };
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent */
        .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
-       .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+       .flags          = ENABLE_REG_32BIT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = USB_HOST_HHC_UHOST_EN,
 };
        /* Direct from ULPD, no parent */
        .rate           = 48000000,
        /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
-       .flags          = RATE_FIXED | ENABLE_REG_32BIT,
+       .flags          = ENABLE_REG_32BIT,
        .enable_reg     = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
        .enable_bit     = 8 /* UHOST_EN */,
 };
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent */
        .rate           = 48000000,
-       .flags          = RATE_FIXED,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
        .enable_bit     = 4,
 };
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent */
        .rate           = 48000000,
-       .flags          = RATE_FIXED,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
        .enable_bit     = 8,
 };
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
        .rate           = 12000000,
-       .flags          = RATE_FIXED,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
        .enable_bit     = 6,
 };
        .ops            = &clkops_generic,
        /* Direct from ULPD, no parent. May be enabled by ext hardware. */
        .rate           = 12000000,
-       .flags          = RATE_FIXED,
 };
 
 static struct clk bclk_16xx = {
        /* Functional clock is direct from ULPD, interface clock is ARMPER */
        .parent         = &armper_ck.clk,
        .rate           = 48000000,
-       .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+       .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = 23,
 };
        /* Functional clock is direct from ULPD, interface clock is ARMPER */
        .parent         = &armper_ck.clk,
        .rate           = 48000000,
-       .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+       .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
        .enable_bit     = 20,
 };
        /* Functional clock is direct from ULPD, interface clock is ARMPER */
        .parent         = &armper_ck.clk,
        .rate           = 48000000,
-       .flags          = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
+       .flags          = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
        .enable_reg     = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
        .enable_bit     = 12,
 };
 
        if (clk->round_rate)
                return clk->round_rate(clk, rate);
 
-       if (clk->flags & RATE_FIXED)
-               printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
-                      "on fixed-rate clock %s\n", clk->name);
-
        return clk->rate;
 }
 
 
        .name           = "func_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32000,
-       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
        .name           = "secure_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32768,
-       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
        .name           = "alt_ck",
        .ops            = &clkops_null,
        .rate           = 54000000,
-       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
        .ops            = &clkops_apll96,
        .parent         = &sys_ck,
        .rate           = 96000000,
-       .flags          = RATE_FIXED | ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
        .ops            = &clkops_apll54,
        .parent         = &sys_ck,
        .rate           = 54000000,
-       .flags          = RATE_FIXED | ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 
        .name           = "func_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32000,
-       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
        .name           = "secure_32k_ck",
        .ops            = &clkops_null,
        .rate           = 32768,
-       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
        .name           = "alt_ck",
        .ops            = &clkops_null,
        .rate           = 54000000,
-       .flags          = RATE_FIXED,
        .clkdm_name     = "wkup_clkdm",
 };
 
        .ops            = &clkops_apll96,
        .parent         = &sys_ck,
        .rate           = 96000000,
-       .flags          = RATE_FIXED | ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
        .ops            = &clkops_apll54,
        .parent         = &sys_ck,
        .rate           = 54000000,
-       .flags          = RATE_FIXED | ENABLE_ON_INIT,
+       .flags          = ENABLE_ON_INIT,
        .clkdm_name     = "wkup_clkdm",
        .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
        .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 
        .name           = "omap_32k_fck",
        .ops            = &clkops_null,
        .rate           = 32768,
-       .flags          = RATE_FIXED,
 };
 
 static struct clk secure_32k_fck = {
        .name           = "secure_32k_fck",
        .ops            = &clkops_null,
        .rate           = 32768,
-       .flags          = RATE_FIXED,
 };
 
 /* Virtual source clocks for osc_sys_ck */
        .name           = "virt_12m_ck",
        .ops            = &clkops_null,
        .rate           = 12000000,
-       .flags          = RATE_FIXED,
 };
 
 static struct clk virt_13m_ck = {
        .name           = "virt_13m_ck",
        .ops            = &clkops_null,
        .rate           = 13000000,
-       .flags          = RATE_FIXED,
 };
 
 static struct clk virt_16_8m_ck = {
        .name           = "virt_16_8m_ck",
        .ops            = &clkops_null,
        .rate           = 16800000,
-       .flags          = RATE_FIXED,
 };
 
 static struct clk virt_19_2m_ck = {
        .name           = "virt_19_2m_ck",
        .ops            = &clkops_null,
        .rate           = 19200000,
-       .flags          = RATE_FIXED,
 };
 
 static struct clk virt_26m_ck = {
        .name           = "virt_26m_ck",
        .ops            = &clkops_null,
        .rate           = 26000000,
-       .flags          = RATE_FIXED,
 };
 
 static struct clk virt_38_4m_ck = {
        .name           = "virt_38_4m_ck",
        .ops            = &clkops_null,
        .rate           = 38400000,
-       .flags          = RATE_FIXED,
 };
 
 static const struct clksel_rate osc_sys_12m_rates[] = {
        .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
        .clksel         = osc_sys_clksel,
        /* REVISIT: deal with autoextclkmode? */
-       .flags          = RATE_FIXED,
        .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk rmii_ck = {
        .name           = "rmii_ck",
        .ops            = &clkops_null,
-       .flags          = RATE_FIXED,
        .rate           = 50000000,
 };
 
 static struct clk pclk_ck = {
        .name           = "pclk_ck",
        .ops            = &clkops_null,
-       .flags          = RATE_FIXED,
        .rate           = 27000000,
 };
 
 
 extern const struct clkops clkops_null;
 
 /* Clock flags */
-#define RATE_FIXED             (1 << 0)        /* Fixed clock rate */
-#define ENABLE_REG_32BIT       (1 << 1)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL     (1 << 2)
-#define CLOCK_NO_IDLE_PARENT   (1 << 3)
-#define ENABLE_ON_INIT         (1 << 4)        /* Enable upon framework init */
-#define INVERT_ENABLE          (1 << 5)        /* 0 enables, 1 disables */
-#define ALWAYS_ENABLED         (1 << 6)
+#define ENABLE_REG_32BIT       (1 << 0)        /* Use 32-bit access */
+#define CLOCK_IDLE_CONTROL     (1 << 1)
+#define CLOCK_NO_IDLE_PARENT   (1 << 2)
+#define ENABLE_ON_INIT         (1 << 3)        /* Enable upon framework init */
+#define INVERT_ENABLE          (1 << 4)        /* 0 enables, 1 disables */
+#define ALWAYS_ENABLED         (1 << 5)
 
 /* Clksel_rate flags */
 #define DEFAULT_RATE           (1 << 0)