drm/i915: pass dev_priv explicitly to DSPFW2

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPFW2 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ba349f90b6614605c52f58ae048961c7b4da4495.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 99f3748209dbf8a8c3d9b268055ce99d8ab7878b..2e24aed3d67cfd612a611295e0c12f217efe3a41 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -725,7 +725,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv,
                           FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
                           FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
                           FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
-       intel_uncore_write(&dev_priv->uncore, DSPFW2,
+       intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
                           (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
                           FW_WM(wm->sr.fbc, FBC_SR) |
                           FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
@@ -775,7 +775,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
                           FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
                           FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
                           FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
-       intel_uncore_write(&dev_priv->uncore, DSPFW2,
+       intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
                           FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
                           FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
                           FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
@@ -2072,8 +2072,9 @@ static void i965_update_wm(struct drm_i915_private *dev_priv)
                           FW_WM(8, CURSORB) |
                           FW_WM(8, PLANEB) |
                           FW_WM(8, PLANEA));
-       intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) |
-                  FW_WM(8, PLANEC_OLD));
+       intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv),
+                          FW_WM(8, CURSORA) |
+                          FW_WM(8, PLANEC_OLD));
        /* update cursor SR watermark */
        intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
 
@@ -3528,7 +3529,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv,
        wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
        wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
 
-       tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
+       tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
        wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
        wm->sr.fbc = _FW_WM(tmp, FBC_SR);
        wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
@@ -3568,7 +3569,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
        wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
        wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
 
-       tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2);
+       tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv));
        wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
        wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
        wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8380cb1309ffcba4cf956a0f93bfd2c8ab37a98e..fd0be33c1864e05fd76ecfe4bb48a915590384f0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1949,7 +1949,7 @@
 #define   DSPFW_PLANEA_SHIFT           0
 #define   DSPFW_PLANEA_MASK            (0x7f << 0)
 #define   DSPFW_PLANEA_MASK_VLV                (0xff << 0) /* vlv/chv */
-#define DSPFW2         _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
+#define DSPFW2(dev_priv)               _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
 #define   DSPFW_FBC_SR_EN              (1 << 31)         /* g4x */
 #define   DSPFW_FBC_SR_SHIFT           28
 #define   DSPFW_FBC_SR_MASK            (0x7 << 28) /* g4x */