struct a6xx_gpu_state_obj *cx_debugbus;
        int nr_cx_debugbus;
 
+       struct msm_gpu_state_bo *gmu_log;
+
        struct list_head objs;
 };
 
                &a6xx_state->gmu_registers[2], false);
 }
 
+static void a6xx_get_gmu_log(struct msm_gpu *gpu,
+               struct a6xx_gpu_state *a6xx_state)
+{
+       struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+       struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
+       struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
+       struct msm_gpu_state_bo *gmu_log;
+
+       gmu_log = state_kcalloc(a6xx_state,
+               1, sizeof(*a6xx_state->gmu_log));
+       if (!gmu_log)
+               return;
+
+       gmu_log->iova = gmu->log.iova;
+       gmu_log->size = gmu->log.size;
+       gmu_log->data = kvzalloc(gmu_log->size, GFP_KERNEL);
+       if (!gmu_log->data)
+               return;
+
+       memcpy(gmu_log->data, gmu->log.virt, gmu->log.size);
+
+       a6xx_state->gmu_log = gmu_log;
+}
+
 #define A6XX_GBIF_REGLIST_SIZE   1
 static void a6xx_get_registers(struct msm_gpu *gpu,
                struct a6xx_gpu_state *a6xx_state,
 
        a6xx_get_gmu_registers(gpu, a6xx_state);
 
+       a6xx_get_gmu_log(gpu, a6xx_state);
+
        /* If GX isn't on the rest of the data isn't going to be accessible */
        if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
                return &a6xx_state->base;
        struct a6xx_gpu_state *a6xx_state = container_of(state,
                        struct a6xx_gpu_state, base);
 
+       if (a6xx_state->gmu_log && a6xx_state->gmu_log->data)
+               kvfree(a6xx_state->gmu_log->data);
+
        list_for_each_entry_safe(obj, tmp, &a6xx_state->objs, node)
                kfree(obj);
 
 
        adreno_show(gpu, state, p);
 
+       drm_puts(p, "gmu-log:\n");
+       if (a6xx_state->gmu_log) {
+               struct msm_gpu_state_bo *gmu_log = a6xx_state->gmu_log;
+
+               drm_printf(p, "    iova: 0x%016llx\n", gmu_log->iova);
+               drm_printf(p, "    size: %d\n", gmu_log->size);
+               adreno_show_object(p, &gmu_log->data, gmu_log->size,
+                               &gmu_log->encoded);
+       }
+
        drm_puts(p, "registers:\n");
        for (i = 0; i < a6xx_state->nr_registers; i++) {
                struct a6xx_gpu_state_obj *obj = &a6xx_state->registers[i];