enum amd_pp_sensors {
        AMDGPU_PP_SENSOR_GFX_SCLK = 0,
+       AMDGPU_PP_SENSOR_CPU_CLK,
        AMDGPU_PP_SENSOR_VDDNB,
        AMDGPU_PP_SENSOR_VDDGFX,
        AMDGPU_PP_SENSOR_UVD_VCLK,
 
 #include <linux/hwmon-sysfs.h>
 #include <linux/nospec.h>
 #include <linux/pm_runtime.h>
+#include <asm/processor.h>
 #include "hwmgr.h"
 
 static const struct cg_flag_name clocks[] = {
  */
 #if defined(CONFIG_DEBUG_FS)
 
+static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
+                                          struct amdgpu_device *adev) {
+       uint16_t *p_val;
+       uint32_t size;
+       int i;
+
+       if (is_support_cclk_dpm(adev)) {
+               p_val = kcalloc(boot_cpu_data.x86_max_cores, sizeof(uint16_t),
+                               GFP_KERNEL);
+
+               if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
+                                           (void *)p_val, &size)) {
+                       for (i = 0; i < boot_cpu_data.x86_max_cores; i++)
+                               seq_printf(m, "\t%u MHz (CPU%d)\n",
+                                          *(p_val + i), i);
+               }
+
+               kfree(p_val);
+       }
+}
+
 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
 {
        uint32_t value;
        /* GPU Clocks */
        size = sizeof(value);
        seq_printf(m, "GFX Clocks and Power:\n");
+
+       amdgpu_debugfs_prints_cpu_info(m, adev);
+
        if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
                seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
        if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
 
        METRICS_CURR_DCLK1,
        METRICS_CURR_FCLK,
        METRICS_CURR_DCEFCLK,
+       METRICS_AVERAGE_CPUCLK,
        METRICS_AVERAGE_GFXCLK,
        METRICS_AVERAGE_SOCCLK,
        METRICS_AVERAGE_FCLK,
 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
 
 bool is_support_sw_smu(struct amdgpu_device *adev);
+bool is_support_cclk_dpm(struct amdgpu_device *adev);
 int smu_reset(struct smu_context *smu);
 int smu_sys_get_pp_table(struct smu_context *smu, void **table);
 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size);
 
        return false;
 }
 
+bool is_support_cclk_dpm(struct amdgpu_device *adev)
+{
+       struct smu_context *smu = &adev->smu;
+
+       if (!is_support_sw_smu(adev))
+               return false;
+
+       if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
+               return false;
+
+       return true;
+}
+
+
 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 {
        struct smu_table_context *smu_table = &smu->smu_table;
 
 #include "soc15_common.h"
 #include "asic_reg/gc/gc_10_3_0_offset.h"
 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
+#include <asm/processor.h>
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
        case METRICS_VOLTAGE_VDDSOC:
                *value = metrics->Voltage[1];
                break;
+       case METRICS_AVERAGE_CPUCLK:
+               memcpy(value, &metrics->CoreFrequency[0],
+                      boot_cpu_data.x86_max_cores * sizeof(uint16_t));
+               break;
        default:
                *value = UINT_MAX;
                break;
                                                   (uint32_t *)data);
                *size = 4;
                break;
+       case AMDGPU_PP_SENSOR_CPU_CLK:
+               ret = vangogh_get_smu_metrics_data(smu,
+                                                  METRICS_AVERAGE_CPUCLK,
+                                                  (uint32_t *)data);
+               *size = boot_cpu_data.x86_max_cores * sizeof(uint16_t);
+               break;
        default:
                ret = -EOPNOTSUPP;
                break;